Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path

Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review

24 Citations (Scopus)


This paper presents a high-throughput and ultralow-power asynchronous domino logic pipeline design method, targeting to latch-free and extremely fine-grain OR gate-level design. The data paths are composed of a mixture of dual-rail and single-rail domino gates. Dual-rail domino gates are limited to construct a stable critical data path. Based on this critical data path, the handshake circuits are greatly simplified, which offers the pipeline high throughput as well as low power consumption. Moreover, the stable critical data path enables the adoption of single-rail domino gates in the noncritical data paths. This further saves a lot of power by reducing the overhead of logic circuits. An 8 × 8 array style multiplier is used for evaluating the proposed pipeline method. Compared with a bundled-data asynchronous domino logic pipeline, the proposed pipeline, respectively, saves up to 60.2% and 24.5% of energy in the best case and the worst case when processing different data patterns.

Original languageEnglish
Article number6802427
Pages (from-to)619-630
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number4
Publication statusPublished - 2015 Apr 1


  • Asynchronous pipeline
  • critical data path
  • dual-rail domino gate
  • single-rail domino gate

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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