ASIC implementation of frequency domain equalizer for single carrier transmission

Kazuhiro Komatsu, Suguru Kameda, Makoto Iwata, Shoichi Tanifuji, Noriharu Suematsu, Tadashi Takagi, Kazuo Tsubouchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Since single-carrier (SC) transmission using frequency domain equalization (FDE) with minimum mean square error (MMSE) operates at lower peak-to-average power ratio (PAPR) than orthogonal frequency division multiplexing (OFDM), SC-FDE with MMSE is a main candidate for uplink of cellular system such as long term evolution (LTE). In this paper, an application specific integrated circuit (ASIC) chip for the SC-FDE is implemented on Taiwan Semiconductor Manufacturing Company (TSMC) 180 nm complementary metal-oxide semiconductor (CMOS). The chip size is 5.86 mm2. The power consumption is 200 mW at data rate of 4.86 Mbit/s. In the condition of 16 paths uniform power delay profile, at a bit error rate (BER) of 10-4, the degradation of measured E b/N0 from computer simulation is found to be less than 1 dB.

Original languageEnglish
Title of host publication2011 30th URSI General Assembly and Scientific Symposium, URSIGASS 2011
DOIs
Publication statusPublished - 2011 Nov 21
Event2011 30th URSI General Assembly and Scientific Symposium, URSIGASS 2011 - Istanbul, Turkey
Duration: 2011 Aug 132011 Aug 20

Publication series

Name2011 30th URSI General Assembly and Scientific Symposium, URSIGASS 2011

Other

Other2011 30th URSI General Assembly and Scientific Symposium, URSIGASS 2011
Country/TerritoryTurkey
CityIstanbul
Period11/8/1311/8/20

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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