Arithmetic semicustom VLSI based on module array structure

Michitaka Kameyama, Masahiro Nomura, Tatsuo Higuchi

Research output: Contribution to conferencePaperpeer-review

Abstract

A novel arithmetic VLSI array based on a signed-digit (SD) arithmetic module is proposed. The module is a universal building block mainly composed of an SD adder. Any arithmetic operations based on addition, subtraction, and multiplication can be realized by appropriately specifying the interconnections between the modules. This module array is much more useful for design and fabrication with short turnaround time than the gate array. High-speed operations can be expected in the adder-based module independently of the word length. Moreover, multiple-valued bidirectional current-mode circuits are effectively employed for the compact implementation of the SD arithmetic VLSI.

Original languageEnglish
Pages101-102
Number of pages2
Publication statusPublished - 1991 Dec 1
Event1991 Symposium on VLSI Circuits - Oiso, Jpn
Duration: 1991 May 301991 Jun 1

Other

Other1991 Symposium on VLSI Circuits
CityOiso, Jpn
Period91/5/3091/6/1

ASJC Scopus subject areas

  • Engineering(all)

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