A new logic-in-memory architecture, in which storage elements are distributed over a current-mode logic-circuit plane by the use of floating-gate MOS transistors, is proposed to realize a compact arithmetic VLSI system. Since not only a storage function but also a voltage-mode linear summation and a voltage-to-current conversion are merged into a single floating-gate MOS transistor, the logic-in-memory VLSI becomes very compact with a high-performance capability. As an example, it is demonstrated that the effective chip area of the proposed four-valued current-mode full adder is reduced to 5% under the same switching speed in comparison with the corresponding binary CMOS implementation.
|Number of pages||6|
|Journal||Proceedings of The International Symposium on Multiple-Valued Logic|
|Publication status||Published - 2000 Jan 1|
|Event||ISMVL'2000 - 30th IEEE International Symposium on Multiple-Valued Logic - Portland, OR, USA|
Duration: 2000 May 23 → 2000 May 25
ASJC Scopus subject areas
- Computer Science(all)