Arithmetic module generator with algorithm optimization capability

Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents an arithmetic module generator based on an arithmetic description language called ARITH. The use of ARITH makes it possible to describe a wide variety of arithmetic algorithms in a unified manner. The ARITH descriptions are formally verified in the generator even if the arithmetic algorithms include unconventional number systems for operands or internal variables. The proposed generator also optimizes arithmetic algorithms by using performance profiles derived from the previous generation. From these features, we can obtain high-performance arithmetic modules whose functions are completely verified at the algorithm level. In this paper, we demonstrate that the optimal prefix adders improved the performance of generated arithmetic modules such as multipliers in comparison with the standard prefix adders.

Original languageEnglish
Title of host publication2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Pages1796-1799
Number of pages4
DOIs
Publication statusPublished - 2008 Sep 19
Event2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
Duration: 2008 May 182008 May 21

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
CountryUnited States
CitySeattle, WA
Period08/5/1808/5/21

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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