Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

A compact lookup table (LUT) circuit using spin transfer-torque magnetic tunnel junction (STT-MTJ) devices combined with MOS transistors is proposed for a standby-power-free field-programmable gate array (FPGA). Since STT-MTJ devices essentially have an asymmetric characteristic in switching currents, one of two write-control transistors can be implemented with a small feature size, while the width of the other one is still large. By sharing the large size of write-control transistor, almost all the transistor size in the proposed LUT circuit becomes small. In fact, the effective silicon area of the proposed write-control transistors for a 6-input LUT circuit is reduced to 68 % in comparison with that of a conventional nonvolatile LUT circuit without applying the asymmetric transistor sizing.

Original languageEnglish
Title of host publication2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
Pages334-337
Number of pages4
DOIs
Publication statusPublished - 2012 Oct 16
Event2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012 - Boise, ID, United States
Duration: 2012 Aug 52012 Aug 8

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Other

Other2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
CountryUnited States
CityBoise, ID
Period12/8/512/8/8

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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