Architecture of an FPGA-based heterogeneous system for code-search problems

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Code search problems refer to searching a particular bit pattern that satisfies given constraints. Obtaining such codes is very important in fields such as data encoding, error correcting, cryptography, etc. Unfortunately, the search time increases exponentially with the number of bits in the code, and typically requires many months of computation to find large codes. On the other hand, the search method mostly consists of 1-bit computations, so that reconfigurable hardware such as FPGAs (field programmable gate arrays) can be used to successfully obtain a massive degree of parallelism. In this paper, we propose a heterogeneous system with a CPU and an FPGA to speed-up code search problems. According to the evaluation, we obtain over 86 times speed-up compared to typical CPU-based implementation for extremal doubly even self-dual code search problem of length 128.

Original languageEnglish
Title of host publicationSupercomputing Frontiers - 4th Asian Conference, SCFA 2018, Proceedings
EditorsRio Yokota, Weigang Wu
PublisherSpringer Verlag
Number of pages10
ISBN (Print)9783319699523
Publication statusPublished - 2018
Event4th Asian Conference on Supercomputing Frontiers, SCFA 2018 - Singapore, Singapore
Duration: 2018 Mar 262018 Mar 29

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume10776 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Other4th Asian Conference on Supercomputing Frontiers, SCFA 2018

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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