Abstract
This paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design. The handshakecomponent- based design is suitable for large-scale, complex asynchronous circuit because of its understandability. This paper proposes an areaefficient architecture of an FPGA that is suitable for handshake-componentbased asynchronous circuit. Moreover, the Four-Phase Dual-Rail encoding is employed to construct circuits robust to delay variation because the data paths are programmable in FPGA. The FPGA based on the proposed architecture is implemented in a 65 nm process. Its evaluation results show that the proposed FPGA can implement handshake components efficiently.
Original language | English |
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Pages (from-to) | 1632-1644 |
Number of pages | 13 |
Journal | IEICE Transactions on Information and Systems |
Volume | E96-D |
Issue number | 8 |
DOIs | |
Publication status | Published - 2013 |
Keywords
- Asynchronous circuit
- FPGA
- Reconfigurable LSI
- Self-timed circuit
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Computer Vision and Pattern Recognition
- Electrical and Electronic Engineering
- Artificial Intelligence