Architecture of a stereo matching VLSI processor based on hierarchically parallel memory access

Masanori Hariyama; Haruka Sasaki; Michitaka Kameyama

doi:10.1093/ietisy/e88-d.7.1486

Architecture of a stereo matching VLSI processor based on hierarchically parallel memory access

Masanori Hariyama, Haruka Sasaki, Michitaka Kameyama

INF - Computer and Mathematical Sciences

Research output: Contribution to journal › Article › peer-review

12 Citations (Scopus)

Abstract

This paper presents a VLSI processor for high-speed and reliable stereo matching based on adaptive window-size control of SAD(Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using multi-resolution images. Parallel memory access is essential for highly parallel image processing. For parallel memory access, this paper also presents an optimal memory allocation that minimizes the hardware amount under the condition of parallel memory access at specified resolutions.

Original language	English
Pages (from-to)	1486-1491
Number of pages	6
Journal	IEICE Transactions on Information and Systems
Volume	E88-D
Issue number	7
DOIs	https://doi.org/10.1093/ietisy/e88-d.7.1486
Publication status	Published - 2005 Jul

Keywords

Logic-in-memory architecture
Memory allocation
SAD (sum of absolute differences)
Stereo vision

ASJC Scopus subject areas

Software
Hardware and Architecture
Computer Vision and Pattern Recognition
Electrical and Electronic Engineering
Artificial Intelligence

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10.1093/ietisy/e88-d.7.1486

Cite this

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AB - This paper presents a VLSI processor for high-speed and reliable stereo matching based on adaptive window-size control of SAD(Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using multi-resolution images. Parallel memory access is essential for highly parallel image processing. For parallel memory access, this paper also presents an optimal memory allocation that minimizes the hardware amount under the condition of parallel memory access at specified resolutions.

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KW - Memory allocation

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KW - Stereo vision

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Architecture of a stereo matching VLSI processor based on hierarchically parallel memory access

Abstract

Keywords

ASJC Scopus subject areas

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