Architecture of a stereo matching VLSI processor based on hierarchically parallel memory access

Masanori Hariyama, Haruka Sasaki, Michitaka Kameyama

Research output: Contribution to journalConference article

8 Citations (Scopus)

Abstract

This paper presents a VLSI processor for high-speed and reliable stereo matching based on adaptive window-size control of SAD(Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using multi-resolution images. Parallel memory access is essential for highly parallel image processing. For parallel memory access, this paper also presents an optimal memory allocation that minimizes the hardware amount under the condition of parallel memory access at specified resolutions.

Original languageEnglish
Pages (from-to)II245-II247
JournalMidwest Symposium on Circuits and Systems
Volume2
Publication statusPublished - 2004 Dec 1
EventThe 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings - Hiroshima, Japan
Duration: 2004 Jul 252004 Jul 28

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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