Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal

Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use of a hybrid multiple-valued/binary context switching signal that eliminates redundancy of a conventional multi-context (MC) switch with high scalability. The transistor count of the proposed MC-switch is reduced to 7% in comparison with that of a SRAM-based one.

Original languageEnglish
Title of host publication20th International Parallel and Distributed Processing Symposium, IPDPS 2006
PublisherIEEE Computer Society
ISBN (Print)1424400546, 9781424400546
DOIs
Publication statusPublished - 2006 Jan 1
Event20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006 - Rhodes Island, Greece
Duration: 2006 Apr 252006 Apr 29

Publication series

Name20th International Parallel and Distributed Processing Symposium, IPDPS 2006
Volume2006

Other

Other20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006
CountryGreece
CityRhodes Island
Period06/4/2506/4/29

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal'. Together they form a unique fingerprint.

Cite this