Architecture and implementation of an associative memory using sparse clustered networks

Hooman Jarollahi; Naoya Onizawa; Vincent Gripon; Warren J. Gross

doi:10.1109/ISCAS.2012.6271922

Architecture and implementation of an associative memory using sparse clustered networks

Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross

Research output: Contribution to conference › Paper › peer-review

23 Citations (Scopus)

Abstract

Associative memories are alternatives to indexed memories that when implemented in hardware can benefit many applications such as data mining. The classical neural network based methodology is impractical to implement since in order to increase the size of the memory, the number of information bits stored per memory bit (efficiency) approaches zero. In addition, the length of a message to be stored and retrieved needs to be the same size as the number of nodes in the network causing the total number of messages the network is capable of storing (diversity) to be limited. Recently, a novel algorithm based on sparse clustered neural networks has been proposed that achieves nearly optimal efficiency and large diversity. In this paper, a proof-of-concept hardware implementation of these networks is presented. The limitations and possible future research areas are discussed.

Original language	English
Pages	2901-2904
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271922
Publication status	Published - 2012
Externally published	Yes
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 2012 May 20 → 2012 May 23

Other

Other	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country	Korea, Republic of
City	Seoul
Period	12/5/20 → 12/5/23

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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