Application of symbolic computer algebra to arithmetic circuit verification

Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Abstract

This paper presents a formal approach to verify arithmetic circuits using symbolic computer algebra. Our method describes arithmetic circuits directly with high-level mathematical objects based on weighted number systems and arithmetic formulae. Such circuit description can be effectively verified by polynomial reduction techniques using Gröbner Bases. In this paper, we describe how the symbolic computer algebra can be used to describe and verify arithmetic circuits. The advantageous effects of the proposed approach are demonstrated through experimental verification of some arithmetic circuits such as multiply-accumulator and FIR filter. The result shows that the proposed approach has a definite possibility of verifying practical arithmetic circuits where the conventional techniques failed.

Original languageEnglish
Title of host publication2007 IEEE International Conference on Computer Design, ICCD 2007
Pages25-32
Number of pages8
DOIs
Publication statusPublished - 2007 Dec 1
Event2007 IEEE International Conference on Computer Design, ICCD 2007 - Lake Tahoe, CA, United States
Duration: 2007 Oct 72007 Oct 10

Publication series

Name2007 IEEE International Conference on Computer Design, ICCD 2007

Other

Other2007 IEEE International Conference on Computer Design, ICCD 2007
CountryUnited States
CityLake Tahoe, CA
Period07/10/707/10/10

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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