Analysis of intrinsic and parasitic gate delay of InGaAs HEMTs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, the principles, measurement techniques, and analysis of the gate delay of high-electron-mobility-transistors (HEMTs) mainly based on an InP material system are discussed. In the measurement techniques, de-embedding of the pad parasitics is also described. The intrinsic part of the gate delay of HEMTs is the transit time for electrons to travel in the gate depletion region. When the gate length is large enough, the intrinsic gate delay is dominant in the total gate delay. However, as the gate length becomes less than 100 nm, the delay analysis reveals that the intrinsic gate delay is now no longer dominant but the parasitic gate delay ascribed to the resistance and capacitance out of the gate region. Based on these results, ways for further improvement of the frequency response are also discussed.

Original languageEnglish
Title of host publicationECS Transactions - State-of-the-Art Program on Compound Semiconductors 49 (SOTAPOCS 49) -and- Nitrides and Wide-Bandgap Semiconductors for Sensors, Photonics, and Electronics 9
Pages65-72
Number of pages8
Edition7
DOIs
Publication statusPublished - 2008 Dec 1
EventState-of-the-Art Program on Compound Semiconductors 49 (SOTAPOCS 49) -and- Nitrides and Wide-Bandgap Semiconductors for Sensors, Photonics, and Electronics 9 - 214th ECS Meeting - Honolulu, HI, United States
Duration: 2008 Oct 122008 Oct 17

Publication series

NameECS Transactions
Number7
Volume16
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherState-of-the-Art Program on Compound Semiconductors 49 (SOTAPOCS 49) -and- Nitrides and Wide-Bandgap Semiconductors for Sensors, Photonics, and Electronics 9 - 214th ECS Meeting
CountryUnited States
CityHonolulu, HI
Period08/10/1208/10/17

ASJC Scopus subject areas

  • Engineering(all)

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