TY - JOUR
T1 - Analysis of gate delay scaling in In0.7Ga0.3As- channel high electron mobility transistors
AU - Fukuda, Shunsuke
AU - Suemitsu, Tetsuya
AU - Otsuji, Taiichi
AU - Kim, Dae Hyun
AU - Del Alamo, Jesús A.
PY - 2009/4/1
Y1 - 2009/4/1
N2 - The intrinsic and the parasitic gate delay of In0.7Ga 0.3-channel high electron mobility transistors (HEMTs) are analyzed. In this paper, we extract the intrinsic parameters of sub-100-nm gate pseudomorphic InGaAs channel HEMTs and estimate the intrinsic and parasitic gate delay. We discuss how the intrinsic and parasitic gate delay are affected by scaling of the gate length and we estimate the parasitic gate capacitance from this gate delay analysis. We also compare the result of the gate delay analysis with lattice-matched InGaAs-channel HEMTs to examine the effect of use of the pseudomorphic InGaAs channel in the gate delay.
AB - The intrinsic and the parasitic gate delay of In0.7Ga 0.3-channel high electron mobility transistors (HEMTs) are analyzed. In this paper, we extract the intrinsic parameters of sub-100-nm gate pseudomorphic InGaAs channel HEMTs and estimate the intrinsic and parasitic gate delay. We discuss how the intrinsic and parasitic gate delay are affected by scaling of the gate length and we estimate the parasitic gate capacitance from this gate delay analysis. We also compare the result of the gate delay analysis with lattice-matched InGaAs-channel HEMTs to examine the effect of use of the pseudomorphic InGaAs channel in the gate delay.
UR - http://www.scopus.com/inward/record.url?scp=77952540300&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77952540300&partnerID=8YFLogxK
U2 - 10.1143/JJAP.48.04C086
DO - 10.1143/JJAP.48.04C086
M3 - Article
AN - SCOPUS:77952540300
VL - 48
JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
SN - 0021-4922
IS - 4 PART 2
M1 - 04C086
ER -