TY - GEN
T1 - Analysis of faults in reversible computing
AU - Lukac, Martin
AU - Kameyama, Michitaka
AU - Perkowski, Marek
AU - Kerntopf, Pawel
AU - Moraga, Claudio
PY - 2014
Y1 - 2014
N2 - In this paper we describe faults that can occur in reversible circuits. In particular, we focus on comparison of faults that can appear in classical circuits with faults that can occur in quantum technology. The analysis is generalized from the point of view of technologies such as information reversible and energy reversible. We show that contrary to classical non-reversible transistor based circuits, it is necessary to specify what type of reversible circuit we are describing. Moreover the level of faults and their analysis must be revised to precisely capture the effects and properties of quantum gates and quantum circuits. By not doing so the available testing approaches adapted from classical circuits could not be able to properly developed to relevant faults. In addition, if the classical faults are directly applied without revision and modifications, the presented testing procedure would be testing for such faults that cannot physically occur in the given implementation of reversible circuits.
AB - In this paper we describe faults that can occur in reversible circuits. In particular, we focus on comparison of faults that can appear in classical circuits with faults that can occur in quantum technology. The analysis is generalized from the point of view of technologies such as information reversible and energy reversible. We show that contrary to classical non-reversible transistor based circuits, it is necessary to specify what type of reversible circuit we are describing. Moreover the level of faults and their analysis must be revised to precisely capture the effects and properties of quantum gates and quantum circuits. By not doing so the available testing approaches adapted from classical circuits could not be able to properly developed to relevant faults. In addition, if the classical faults are directly applied without revision and modifications, the presented testing procedure would be testing for such faults that cannot physically occur in the given implementation of reversible circuits.
KW - Quantum Faults
KW - Quantum Implementation
KW - Reversible Faults
KW - Reversible Logic
UR - http://www.scopus.com/inward/record.url?scp=84904479782&partnerID=8YFLogxK
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U2 - 10.1109/ISMVL.2014.28
DO - 10.1109/ISMVL.2014.28
M3 - Conference contribution
AN - SCOPUS:84904479782
SN - 9781479935345
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 115
EP - 120
BT - Proceedings - 2014 IEEE 44th International Symposium on Multiple-Valued Logic, ISMVL 2014
PB - IEEE Computer Society
T2 - 44th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2014
Y2 - 19 May 2014 through 21 May 2014
ER -