Analog CMOS implementation of quantized interconnection neural networks for memorizing limit cycles

Cheol Young Park, Koji Nakajima

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

In order to investigate the dynamic behavior of quantized interconnection neural networks on neuro-chips, we have designed and fabricated hardware neural networks according to design rule of a 1. 2 μm CMOS technology. To this end, we have developed programmable synaptic weights for the interconnection with three values of ±1 and 0. We have tested the chip and verified the dynamic behavior of the networks in a circuit level. As a result of our study, we can provide the most straightforward application of networks for a dynamic pattern classifier. The proposed network is advantageous in that it does not need extra exemplar to classify shifted or reversed patterns.

Original languageEnglish
Pages (from-to)952-957
Number of pages6
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE82-A
Issue number6
Publication statusPublished - 1999 Jan 1

Keywords

  • Limit cycles
  • Neural networks
  • Pattern classifier
  • Programmable synapse
  • Quantized interconnection

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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