An operand status based instruction steering scheme for clustered architectures

Yukinori Sato, Kenichi Suzuki, Tadao Nakamura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Clustered architectures which intend to process data within a localized PE are one of the approaches to increase the performance under the difficulties of the wire delay problems. The performance of the clustered architecture depends on the implemented instruction steering scheme. Existing steering schemes insert inter-PE communications to achieve load balance among PEs. These insertions delay the executions of the dependent instructions and lead to the degradation of the performance. In this paper, we propose a novel instruction steering scheme, which gives priority to critical dependencies. The way to find out the critical dependencies is by observing the status of the source operands of an instruction. We evaluate the proposed scheme and compare it with the existing ones. The results show that the proposed scheme outperforms the existing schemes in terms of instruction per clock because of reductions of the critical inter-PE communications with superior load balance among the PEs.

Original languageEnglish
Title of host publicationProceedings of the 2005 International Conference on Computer Design, CDES'05
Pages168-174
Number of pages7
Publication statusPublished - 2005 Dec 1
Event2005 International Conference on Computer Design, CDES'05 - Las Vegas, NV, United States
Duration: 2005 Jun 272005 Jun 30

Publication series

NameProceedings of the 2005 International Conference on Computer Design, CDES'05

Other

Other2005 International Conference on Computer Design, CDES'05
CountryUnited States
CityLas Vegas, NV
Period05/6/2705/6/30

Keywords

  • Clustered architecture
  • Data dependence-based design
  • Instruction steering
  • Instruction-level parallelism

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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