An on-chip glitchy-clock generator for testing fault injection attacks

Sho Endo, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Research output: Contribution to journalArticlepeer-review

43 Citations (Scopus)

Abstract

This paper presents a glitchy-clock generator integrated in FPGA for evaluating fault injection attacks and their countermeasures on cryptographic modules. The proposed generator exploits clock management capabilities, which are common in modern FPGAs, to generate clock signal with temporal voltage spike. The shape and timing of the glitchy-clock cycle are configurable at run time. The proposed generator can be embedded in a single FPGA without any external instrument (e. g., a pulse generator and a variable power supply). Such integration enables reliable and reproducible fault injection experiments. In this paper, we examine the characteristics of the proposed generator through experiments on Side-channel Attack Standard Evaluation Board (SASEBO). The result shows that the timing of the glitches can be controlled at the step of about 0. 17 ns. We also demonstrate its application to the safe-error attack against an RSA processor.

Original languageEnglish
Pages (from-to)265-270
Number of pages6
JournalJournal of Cryptographic Engineering
Volume1
Issue number4
DOIs
Publication statusPublished - 2011 Dec 1

Keywords

  • Clock glitch
  • Fault injection attacks
  • RSA
  • Safe-error attack

ASJC Scopus subject areas

  • Software
  • Computer Networks and Communications

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