An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture

Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small area and low power of function units, while LEDR encoding for high throughput and low power of data transfer. The proposed FPGA is fabricated in the e-Shuttle 65nm CMOS process and operates at 870 MHz. Compared to the synchronous FPGA, the power consumption is reduced by 38% for the workload of 15%.

Original languageEnglish
Title of host publication2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
Pages89-90
Number of pages2
DOIs
Publication statusPublished - 2011 Mar 28
Event2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011 - Yokohama, Japan
Duration: 2011 Jan 252011 Jan 28

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
CountryJapan
CityYokohama
Period11/1/2511/1/28

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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