An impact of circuit scale on the performance of 3-D stacked arithmetic units

Jubee Tada, Ryusuke Egawa, Hiroaki Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Recently, the 3-D stacked integrated circuit technology has been expected to overcome the limitations in the design of the 2-D implemented microprocessors. This paper examines the potential of 3-D integration in design and implementation of large-scale arithmetic units. In this paper, 3-D stacked parallel multipliers with various operand sizes are designed, and the effect of circuit scale on the performance of 3-D stacked multipliers is discussed. In the design of a large-scale parallel multiplier, a lot of through-silicon-vias are required by the conventional partitioning pattern. This paper proposes a partitioning pattern suitable for a large-scale 3-D stacked parallel multiplier. The proposed partitioning pattern aims to reduce the number of TSVs with a large-scale parallel multiplier. Based on the proposed partitioning pattern, 3-D stacked 32, 64, and 128-bit multipliers are designed and evaluated. The proposed partitioning pattern achieves a 13.4% reduction in critical path delay and a 10.4% reduction in power consumption compared to the 2-D implementation, in the case of an 128-bit four-layer implemented 3-D stacked multiplier.

Original languageEnglish
Title of host publication2014 International 3D Systems Integration Conference, 3DIC 2014 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479984725
DOIs
Publication statusPublished - 2014 Jan 1
EventInternational 3D Systems Integration Conference, 3DIC 2014 - Kinsdale, Ireland
Duration: 2014 Dec 12014 Dec 3

Publication series

Name2014 International 3D Systems Integration Conference, 3DIC 2014 - Proceedings

Other

OtherInternational 3D Systems Integration Conference, 3DIC 2014
CountryIreland
CityKinsdale
Period14/12/114/12/3

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Hardware and Architecture

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    Tada, J., Egawa, R., & Kobayashi, H. (2014). An impact of circuit scale on the performance of 3-D stacked arithmetic units. In 2014 International 3D Systems Integration Conference, 3DIC 2014 - Proceedings [07152185] (2014 International 3D Systems Integration Conference, 3DIC 2014 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/3DIC.2014.7152185