An image filtering processor for face/object recognition using merged/ mixed analog-digital architecture

Keisuke Korekado; Takashi Morie; Osamu Nomura; Teppei Nakano; Masakazu Matsugu; Atsushi Iwata

doi:10.1109/VLSIC.2005.1469371

An image filtering processor for face/object recognition using merged/ mixed analog-digital architecture

Keisuke Korekado, Takashi Morie, Osamu Nomura, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata

Research output: Contribution to conference › Paper › peer-review

13 Citations (Scopus)

Abstract

This paper proposes an image-filtering processor LSI based on a hybrid approach using pulse-width modulation (PWM) and digital circuits. The LSI has been designed for implementing convolutional neural networks with a very large convolution-kernel size. The LSI designed using a 0.35 μm CMOS performs 6-bit precision convolutions for an image of 80×80 pixels with a kernel size of up to 51×51 pixels within 8.2 ms. All operations for the fabricated LSI have been successfully verified. The power consumption estimated from SPICE simulation is 280 mW.

Original language	English
Pages	220-223
Number of pages	4
DOIs	https://doi.org/10.1109/VLSIC.2005.1469371
Publication status	Published - 2005
Externally published	Yes
Event	2005 Symposium on VLSI Circuits - Kyoto, Japan Duration: 2005 Jun 16 → 2005 Jun 18

Other

Other	2005 Symposium on VLSI Circuits
Country/Territory	Japan
City	Kyoto
Period	05/6/16 → 05/6/18

Keywords

Convolutional neural network
Image filter
Mixed/merged analog-digital and face/object recognition

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/VLSIC.2005.1469371

Cite this

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title = "An image filtering processor for face/object recognition using merged/ mixed analog-digital architecture",

abstract = "This paper proposes an image-filtering processor LSI based on a hybrid approach using pulse-width modulation (PWM) and digital circuits. The LSI has been designed for implementing convolutional neural networks with a very large convolution-kernel size. The LSI designed using a 0.35 μm CMOS performs 6-bit precision convolutions for an image of 80×80 pixels with a kernel size of up to 51×51 pixels within 8.2 ms. All operations for the fabricated LSI have been successfully verified. The power consumption estimated from SPICE simulation is 280 mW.",

keywords = "Convolutional neural network, Image filter, Mixed/merged analog-digital and face/object recognition",

author = "Keisuke Korekado and Takashi Morie and Osamu Nomura and Teppei Nakano and Masakazu Matsugu and Atsushi Iwata",

year = "2005",

doi = "10.1109/VLSIC.2005.1469371",

language = "English",

pages = "220--223",

note = "2005 Symposium on VLSI Circuits ; Conference date: 16-06-2005 Through 18-06-2005",

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T1 - An image filtering processor for face/object recognition using merged/ mixed analog-digital architecture

AU - Korekado, Keisuke

AU - Morie, Takashi

AU - Nomura, Osamu

AU - Nakano, Teppei

AU - Matsugu, Masakazu

AU - Iwata, Atsushi

PY - 2005

Y1 - 2005

N2 - This paper proposes an image-filtering processor LSI based on a hybrid approach using pulse-width modulation (PWM) and digital circuits. The LSI has been designed for implementing convolutional neural networks with a very large convolution-kernel size. The LSI designed using a 0.35 μm CMOS performs 6-bit precision convolutions for an image of 80×80 pixels with a kernel size of up to 51×51 pixels within 8.2 ms. All operations for the fabricated LSI have been successfully verified. The power consumption estimated from SPICE simulation is 280 mW.

AB - This paper proposes an image-filtering processor LSI based on a hybrid approach using pulse-width modulation (PWM) and digital circuits. The LSI has been designed for implementing convolutional neural networks with a very large convolution-kernel size. The LSI designed using a 0.35 μm CMOS performs 6-bit precision convolutions for an image of 80×80 pixels with a kernel size of up to 51×51 pixels within 8.2 ms. All operations for the fabricated LSI have been successfully verified. The power consumption estimated from SPICE simulation is 280 mW.

KW - Convolutional neural network

KW - Image filter

KW - Mixed/merged analog-digital and face/object recognition

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DO - 10.1109/VLSIC.2005.1469371

M3 - Paper

AN - SCOPUS:33745155806

SP - 220

EP - 223

T2 - 2005 Symposium on VLSI Circuits

Y2 - 16 June 2005 through 18 June 2005

ER -

An image filtering processor for face/object recognition using merged/ mixed analog-digital architecture

Abstract

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Keywords

ASJC Scopus subject areas

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