An image filtering processor for face/object recognition using merged/ mixed analog-digital architecture

Keisuke Korekado, Takashi Morie, Osamu Nomura, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata

Research output: Contribution to conferencePaperpeer-review

12 Citations (Scopus)

Abstract

This paper proposes an image-filtering processor LSI based on a hybrid approach using pulse-width modulation (PWM) and digital circuits. The LSI has been designed for implementing convolutional neural networks with a very large convolution-kernel size. The LSI designed using a 0.35 μm CMOS performs 6-bit precision convolutions for an image of 80×80 pixels with a kernel size of up to 51×51 pixels within 8.2 ms. All operations for the fabricated LSI have been successfully verified. The power consumption estimated from SPICE simulation is 280 mW.

Original languageEnglish
Pages220-223
Number of pages4
DOIs
Publication statusPublished - 2005
Externally publishedYes
Event2005 Symposium on VLSI Circuits - Kyoto, Japan
Duration: 2005 Jun 162005 Jun 18

Other

Other2005 Symposium on VLSI Circuits
Country/TerritoryJapan
CityKyoto
Period05/6/1605/6/18

Keywords

  • Convolutional neural network
  • Image filter
  • Mixed/merged analog-digital and face/object recognition

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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