Abstract
This paper proposes an image-filtering processor LSI based on a hybrid approach using pulse-width modulation (PWM) and digital circuits. The LSI has been designed for implementing convolutional neural networks with a very large convolution-kernel size. The LSI designed using a 0.35 μm CMOS performs 6-bit precision convolutions for an image of 80×80 pixels with a kernel size of up to 51×51 pixels within 8.2 ms. All operations for the fabricated LSI have been successfully verified. The power consumption estimated from SPICE simulation is 280 mW.
Original language | English |
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Pages | 220-223 |
Number of pages | 4 |
DOIs | |
Publication status | Published - 2005 |
Externally published | Yes |
Event | 2005 Symposium on VLSI Circuits - Kyoto, Japan Duration: 2005 Jun 16 → 2005 Jun 18 |
Other
Other | 2005 Symposium on VLSI Circuits |
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Country/Territory | Japan |
City | Kyoto |
Period | 05/6/16 → 05/6/18 |
Keywords
- Convolutional neural network
- Image filter
- Mixed/merged analog-digital and face/object recognition
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering