An FPGA-oriented motion-stereo processor with a simple interconnection network for parallel memory access

Seunghwan Lee, Masanori Hariyama, Michitaka Kameyama

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

In designing a field-programmable gate array (FPGA)-based processor for motion stereo, a parallel memory system and a simple interconnection network for parallel data transfer are essential for parallel image processing. This paper, firstly, presents an FPGA-oriented hierarchical memory system. To reduce the bandwidth requirement between an on-chip memory in an FPGA and external memories, we propose an efficient scheduling: Once pixels are transferred to the on-chip memory, operations associated with the data are consecutively performed. Secondly, a rectangular memory allocation is proposed which allocates pixels to be accessed in parallel onto different memory modules of the on-chip memory. Consequently, completely parallel access can be achieved. The memory allocation also minimizes the required capacity of the on-chip memory and thus is suitable for FPGA-based implementation. Finally, a functional unit allocation is proposed to minimize the complexity between memory modules and functional units. An experimental result shows that the performance of the processor becomes 96 times higher than that of a 400 MHz Pentium II.

Original languageEnglish
Pages (from-to)2122-2129
Number of pages8
JournalIEICE Transactions on Information and Systems
VolumeE83-D
Issue number12
Publication statusPublished - 2000 Jan 1

Keywords

  • Fpga-based processor
  • Functional unit allocation
  • Memory allocation
  • Motion stereo

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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