An Experimental 2-bit/Cell Storage DRAM for Macroce11 or Memory-on-Logic Application

Tohru Furuyama, Takashi Ohsawa, Yohji Watanabe, Kazuyoshi Muraoka, Kenji Natori, Yousei Nagahama, Tohru Kimura, Hiroto Tanaka

    Research output: Contribution to journalArticle

    17 Citations (Scopus)

    Abstract

    A novel 2-bit (four-level)/cell storage technique is described. This technique saves the RAM area, in particular the cell array area which is highly defect sensitive provides fairly fast access time. An experimental 1-Mbit DRAM has been fabricated and has successfully demon-strated the feasibility of this technique for embedded memory applications.

    Original languageEnglish
    Pages (from-to)388-393
    Number of pages6
    JournalIEEE Journal of Solid-State Circuits
    Volume24
    Issue number2
    DOIs
    Publication statusPublished - 1989 Apr

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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  • Cite this

    Furuyama, T., Ohsawa, T., Watanabe, Y., Muraoka, K., Natori, K., Nagahama, Y., Kimura, T., & Tanaka, H. (1989). An Experimental 2-bit/Cell Storage DRAM for Macroce11 or Memory-on-Logic Application. IEEE Journal of Solid-State Circuits, 24(2), 388-393. https://doi.org/10.1109/4.18599