A 5-V 4M word x 4-bit dynamic RAM with a 100-MHz serial READ/WRITE mode has been designed and fabricated using 0.7-ism triple-tub CMOS technology. The RAM utilizes a newly developed STT (STacked Trench capacitor) cell which achieved 37 fF in a small cell size of 1.7x 3.6 m2. The STD (Sidewall Transistor with Double doped drain) structure has been introduced for PMOSFET's to realize high-speed operation, and in order to ensure the MOSFET reliability the 5-V external supply voltage is converted to a 4-V internal supply voltage by an on-chip voltage converter circuit. A new on-chip interleaved circuit and double-input-buffer scheme have been introduced to realize a high-speed serial READ/WRITE operation. Using an external 5-V power supply, the RAM achieved a 100-MHz serial access cycle, and the RA S access time is 70 ns. The typical active current is 120 mA at a 190-ns cycle time.
ASJC Scopus subject areas
- Electrical and Electronic Engineering