A new synapse memory cell employing floating-gate EEPROM technology has been developed which is characterized by an excellent weight-updating linearity under the constant-pulse programming. Such a feature has been realized for the first time by employing a simple self-feedback regime in each cell circuitry. The potential of the floating gate is set to the tunneling electrode by the source follower action of the built-in cell circuitry, thus assuring a constant electric field strength in the tunnel oxide at each programming cycle independent of the stored charge in the floating gate. The synapse cell is composed of only seven transistors and inherits all the advanced features of our original six-transistor cell , such as the standby-power free and dual polarity characteristics. In addition, by optimizing the intra-cell coupling capacitance ratios, the acceleration effect in updating the weight has also been accomplished. All these features make the new synapse cell fully compatible with the hardware learning architecture of the Neuron-MOS neural network , . The new synapse cell concept has been verified by experiments using test circuits fabricated by a double-polysilicon CMOS process.
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering