An energy-aware set-level refreshing mechanism for eDRAM last-level caches

Masayuki Sato, Zehua Li, Ryusuke Egawa, Hiroaki Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Since embedded DRAM (eDRAM) has a higher density with a lower leakage power than SRAM, it is promising to be used as the last-level cache (LLC) of a microprocessor. However, an eDRAM LLC needs a high energy consumption for refresh operations. In particular, the conventional eDRAM LLC refreshes even dead cache lines that are not reused until their evictions. This paper proposes an energy-aware set-level refreshing mechanism to reduce the wasted energy due to unnecessary refreshes of dead cache lines. In the case where the cache resources are excessive compared with the demand of an application, the excessive resources are wasted to store dead lines. Therefore, the proposed mechanism dynamically adjusts the number of refreshed cache lines. The evaluation results show that the proposed mechanism can reduce the LLC energy consumption by 46% with a 1% performance loss on average.

Original languageEnglish
Title of host publication21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-3
Number of pages3
ISBN (Electronic)9781538661024
DOIs
Publication statusPublished - 2018 Jun 5
Event21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Yokohama, Japan
Duration: 2018 Apr 182018 Apr 20

Publication series

Name21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings

Other

Other21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018
CountryJapan
CityYokohama
Period18/4/1818/4/20

Keywords

  • cache memory
  • eDRAM cache
  • energy consumption
  • refresh operations

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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