An ASIC implementation of phase correlation based on run-time reconfiguration technique

Naoto Miyamoto, Katsuhiko Hanzawa, Tadahiro Ohmi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we present an application-specific LSI that is designed using a run-time reconfiguration technique. The implemented algorithm is phase correlation. The calculation of phase correlation includes Fast Fourier Transform (FFT) followed by Inverse Fast Fourier Transform (IFFT). We have developed a dual-decimation butterfly module that can be self-reconfigured, at run-time, to be either decimation-in-time (DIT) or decimation-in-frequency (DIF). By sharing the common parts between the DIT and DIF butterfly modules, the dual-decimation butterfly module can reduce the logic size to about half. DIT-mode is used for FFT and DIF-mode is used for IFFT. No data reordering, such as natural-to-reverse or reverse-to-natural conversion, between FFT and IFFT is necessary. As a consequence, the amount of intermediate frame buffers and the number of memory accesses are significantly reduced.

Original languageEnglish
Title of host publicationProceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09
Pages308-311
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 International Conference on Field-Programmable Technology, FPT'09 - Sydney, Australia
Duration: 2009 Dec 92009 Dec 11

Publication series

NameProceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09

Other

Other2009 International Conference on Field-Programmable Technology, FPT'09
Country/TerritoryAustralia
CitySydney
Period09/12/909/12/11

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Hardware and Architecture
  • Software

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