TY - GEN

T1 - An area-efficient multiple-valued reconfigurable vlsi architecture using an x-net

AU - Bai, Xu

AU - Kameyama, Michitaka

PY - 2013

Y1 - 2013

N2 - An X-net is employed for simplifying interconnections and switch blocks of a multiple-valued reconfigurable VLSI (MV-RVLSI). One cell composed of a logic block and a switch block is connected to four adjacent 'X' intersections by four one-bit switches. A multiple-valued X-net data transfer scheme is proposed to improve the utilization of the X-net, where two binary data can be transferred from two adjacent cells to one common adjacent cell simultaneously at each 'X' intersection. To evaluate the MV-RVLSIs, a sum-of-absolute-differences operation is mapped onto a previous MV-RVLSI using an 8 nearest-neighbor mesh network (8-NNM) and the MV-RVLSI using the X-net, respectively. The area of the MV-RVLSI based on the multiple-valued X-net data transfer scheme is reduced to 73% and 84%, respectively, in comparison with those of the MVRVLSI using the 8-NNM and the MV-RVLSI based on a binary X-net data transfer scheme.

AB - An X-net is employed for simplifying interconnections and switch blocks of a multiple-valued reconfigurable VLSI (MV-RVLSI). One cell composed of a logic block and a switch block is connected to four adjacent 'X' intersections by four one-bit switches. A multiple-valued X-net data transfer scheme is proposed to improve the utilization of the X-net, where two binary data can be transferred from two adjacent cells to one common adjacent cell simultaneously at each 'X' intersection. To evaluate the MV-RVLSIs, a sum-of-absolute-differences operation is mapped onto a previous MV-RVLSI using an 8 nearest-neighbor mesh network (8-NNM) and the MV-RVLSI using the X-net, respectively. The area of the MV-RVLSI based on the multiple-valued X-net data transfer scheme is reduced to 73% and 84%, respectively, in comparison with those of the MVRVLSI using the 8-NNM and the MV-RVLSI based on a binary X-net data transfer scheme.

KW - Multiple-valued data transfer scheme

KW - Reconfigurable VLSI architecture

KW - X-net

UR - http://www.scopus.com/inward/record.url?scp=84880737878&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84880737878&partnerID=8YFLogxK

U2 - 10.1109/ISMVL.2013.13

DO - 10.1109/ISMVL.2013.13

M3 - Conference contribution

AN - SCOPUS:84880737878

SN - 9780769549767

T3 - Proceedings of The International Symposium on Multiple-Valued Logic

SP - 272

EP - 277

BT - Proceedings - 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013

T2 - 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013

Y2 - 22 May 2013 through 24 May 2013

ER -