An architecture of small-scaled neuro-hardware using probabilistically coded pulse neurons

Takeshi Kawashima, Akio Ishiguro, Shigeru Okuma

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

In this paper, we present an architecture for neuro-hardware that can be realized in circuits of far smaller scale than in the conventional approach. In order to reduce the scale of the circuits, the architecture employs a new method of computing the membrane potential and the sigmoidal function by encapsulating the probabilistic properties into the relative delay between two pulses. The proposed architecture makes it possible to integrate more than 100 neurons in the latest FPGA chip, which is a 13-fold miniaturization compared to the conventional architecture.

Original languageEnglish
Pages (from-to)48-55
Number of pages8
JournalElectrical Engineering in Japan (English translation of Denki Gakkai Ronbunshi)
Volume139
Issue number4
DOIs
Publication statusPublished - 2002 Jan 1
Externally publishedYes

Keywords

  • Hardware miniaturization
  • Neuro-hardware
  • Probabilistic coding digital circuit
  • Pulsed neuron

ASJC Scopus subject areas

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering

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