An architecture of small-scaled neuro-hardware using probabilistically-coded pulse neurons

T. Kawashima, A. Ishiguro, S. Okuma

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)


We present an architecture of a neuro-hardware that can be realized on a small-scaled circuit compared to the conventional approach. In order to reduce the scale of the circuits, the architecture employs a new method of computing the membrane potential and sigmoid function by encapsulating the probability properties into relative delay between two pulses. The proposed architecture enables one to integrate more than one hundred of neurons on a latest FPGA chip, which means thirteen-fold miniaturization compared to the conventional architecture.

Original languageEnglish
Title of host publicationIECON Proceedings (Industrial Electronics Conference)
PublisherIEEE Computer Society
Number of pages7
Publication statusPublished - 2000 Jan 1
Externally publishedYes

Publication series

NameIECON Proceedings (Industrial Electronics Conference)

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering


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