An architecture of small-scaled neuro-hardware using probabilistically-calculated pulse neurons

Takeshi Kawashima; Akio Ishiguro; Shigeru Okuma

doi:10.1109/ICSMC.2001.973499

An architecture of small-scaled neuro-hardware using probabilistically-calculated pulse neurons

Takeshi Kawashima, Akio Ishiguro, Shigeru Okuma

Research output: Contribution to journal › Article › peer-review

Abstract

This article proposed an architecture of a neuro-hardware that can be realized on by far a small-scaled circuit compared to the conventional approach. In order to reduce the scale of the circuits, the architecture employs a new method of computing the membrane potential and the sigmoidal function by encapsulating the probability properties into relative delay between two pulses of the different signal lines. Proposed architecture enables to integrate more than one hundred of neurons on a latest FPGA chip, which means thirteen-fold miniaturization compared to conventional architecture.

Original language	English
Pages (from-to)	1520-1525
Number of pages	6
Journal	Proceedings of the IEEE International Conference on Systems, Man and Cybernetics
Volume	3
DOIs	https://doi.org/10.1109/ICSMC.2001.973499
Publication status	Published - 2001 Jan 1
Externally published	Yes

Keywords

Digital circuit
Miniaturization
Neuro-hardware
Probabilistically coding
Pulse neuron

ASJC Scopus subject areas

Control and Systems Engineering
Hardware and Architecture

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An architecture of small-scaled neuro-hardware using probabilistically-calculated pulse neurons

Abstract

Keywords

ASJC Scopus subject areas

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