An advanced NAND-structure cell technology for reliable 3.3 V 64 Mb electrically erasable and programmable read only memories (EEPROMs)

An extremely small NAND-structure cell of 1.13 μm² per bit, 80% of the smallest Flash memory cell reported so far [H. Kume et al.: IEEE Tech. Dig. IEDM (1992) p. 99l], has been developed in 0.4 μm technology. The chip size of a 64 Mb NAND electrically erasable and programmable read only memory (EEPROM) using this cell is estimated to be 120 mm², which is 60% that of a 64 Mb DRAM. In order to realize the small cell size, a 0.8 μm field isolation is used. A negative bias of – 0.5 V to the P-well of the memory cell is applied during writing. In addition, a bit-by-bit intelligent writing technology allows a 3.3 V data sensing scheme which can suppress read disturb to 1/1000 in comparison with the conventional 5 V scheme. As a result, it is expected that with this technology, 10⁶ write and erase cycles can be achieved and that the tunnel oxide can be scaled down from 10 nm to 8 nm.