An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches

Masayuki Sato, Zentaro Sakai, Ryusuke Egawa, Hiroaki Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Spin-Transfer Torque RAM (STT-RAM) has a higher density than SRAM and non-volatility, and is expected to be used as the last-level cache (LLC) of a microprocessor. One technical issue is that, since the energy cost of write access requests for an STT-RAM LLC is expensive, the total energy consumption of the STT-RAM LLC may increase for some write-intensive applications. Therefore, this paper proposes an Adjacent-Line-Merging Writeback Scheme. The proposed scheme dynamically merges two adjacent lines and write them back to the STT-RAM LLC as one line. The evaluation results show that the proposed scheme can reduce the energy consumption by up to 28%, and 10.4% on average.

Original languageEnglish
Title of host publicationProceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538638286
DOIs
Publication statusPublished - 2017 Jun 12
Event20th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017 - Yokohama, Japan
Duration: 2017 Apr 192017 Apr 21

Publication series

NameProceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017

Other

Other20th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017
Country/TerritoryJapan
CityYokohama
Period17/4/1917/4/21

Keywords

  • STT-RAM cache
  • cache memory
  • merged writeback
  • write energy

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches'. Together they form a unique fingerprint.

Cite this