TY - GEN
T1 - An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches
AU - Sato, Masayuki
AU - Sakai, Zentaro
AU - Egawa, Ryusuke
AU - Kobayashi, Hiroaki
PY - 2017/6/12
Y1 - 2017/6/12
N2 - Spin-Transfer Torque RAM (STT-RAM) has a higher density than SRAM and non-volatility, and is expected to be used as the last-level cache (LLC) of a microprocessor. One technical issue is that, since the energy cost of write access requests for an STT-RAM LLC is expensive, the total energy consumption of the STT-RAM LLC may increase for some write-intensive applications. Therefore, this paper proposes an Adjacent-Line-Merging Writeback Scheme. The proposed scheme dynamically merges two adjacent lines and write them back to the STT-RAM LLC as one line. The evaluation results show that the proposed scheme can reduce the energy consumption by up to 28%, and 10.4% on average.
AB - Spin-Transfer Torque RAM (STT-RAM) has a higher density than SRAM and non-volatility, and is expected to be used as the last-level cache (LLC) of a microprocessor. One technical issue is that, since the energy cost of write access requests for an STT-RAM LLC is expensive, the total energy consumption of the STT-RAM LLC may increase for some write-intensive applications. Therefore, this paper proposes an Adjacent-Line-Merging Writeback Scheme. The proposed scheme dynamically merges two adjacent lines and write them back to the STT-RAM LLC as one line. The evaluation results show that the proposed scheme can reduce the energy consumption by up to 28%, and 10.4% on average.
KW - STT-RAM cache
KW - cache memory
KW - merged writeback
KW - write energy
UR - http://www.scopus.com/inward/record.url?scp=85022229925&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85022229925&partnerID=8YFLogxK
U2 - 10.1109/CoolChips.2017.7946380
DO - 10.1109/CoolChips.2017.7946380
M3 - Conference contribution
AN - SCOPUS:85022229925
T3 - Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017
BT - Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017
Y2 - 19 April 2017 through 21 April 2017
ER -