An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches

Masayuki Sato; Zentaro Sakai; Ryusuke Egawa; Hiroaki Kobayashi

doi:10.1109/CoolChips.2017.7946380

An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches

Masayuki Sato, Zentaro Sakai, Ryusuke Egawa, Hiroaki Kobayashi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Spin-Transfer Torque RAM (STT-RAM) has a higher density than SRAM and non-volatility, and is expected to be used as the last-level cache (LLC) of a microprocessor. One technical issue is that, since the energy cost of write access requests for an STT-RAM LLC is expensive, the total energy consumption of the STT-RAM LLC may increase for some write-intensive applications. Therefore, this paper proposes an Adjacent-Line-Merging Writeback Scheme. The proposed scheme dynamically merges two adjacent lines and write them back to the STT-RAM LLC as one line. The evaluation results show that the proposed scheme can reduce the energy consumption by up to 28%, and 10.4% on average.

Original language	English
Title of host publication	Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538638286
DOIs	https://doi.org/10.1109/CoolChips.2017.7946380
Publication status	Published - 2017 Jun 12
Event	20th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017 - Yokohama, Japan Duration: 2017 Apr 19 → 2017 Apr 21

Publication series

Name	Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017

Other

Other	20th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017
Country/Territory	Japan
City	Yokohama
Period	17/4/19 → 17/4/21

Keywords

STT-RAM cache
cache memory
merged writeback
write energy

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/CoolChips.2017.7946380

Cite this

Sato, M., Sakai, Z., Egawa, R., & Kobayashi, H. (2017). An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches. In Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017 [7946380] (Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CoolChips.2017.7946380

An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches. / Sato, Masayuki; Sakai, Zentaro; Egawa, Ryusuke; Kobayashi, Hiroaki.

Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 7946380 (Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sato, M, Sakai, Z, Egawa, R & Kobayashi, H 2017, An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches. in Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017., 7946380, Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017, Institute of Electrical and Electronics Engineers Inc., 20th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017, Yokohama, Japan, 17/4/19. https://doi.org/10.1109/CoolChips.2017.7946380

Sato M, Sakai Z, Egawa R, Kobayashi H. An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches. In Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017. Institute of Electrical and Electronics Engineers Inc. 2017. 7946380. (Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017). https://doi.org/10.1109/CoolChips.2017.7946380

Sato, Masayuki ; Sakai, Zentaro ; Egawa, Ryusuke ; Kobayashi, Hiroaki. / An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches. Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017. Institute of Electrical and Electronics Engineers Inc., 2017. (Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017).

@inproceedings{fcbb60f6bccb4877b64edf5503e420f3,

title = "An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches",

abstract = "Spin-Transfer Torque RAM (STT-RAM) has a higher density than SRAM and non-volatility, and is expected to be used as the last-level cache (LLC) of a microprocessor. One technical issue is that, since the energy cost of write access requests for an STT-RAM LLC is expensive, the total energy consumption of the STT-RAM LLC may increase for some write-intensive applications. Therefore, this paper proposes an Adjacent-Line-Merging Writeback Scheme. The proposed scheme dynamically merges two adjacent lines and write them back to the STT-RAM LLC as one line. The evaluation results show that the proposed scheme can reduce the energy consumption by up to 28%, and 10.4% on average.",

keywords = "STT-RAM cache, cache memory, merged writeback, write energy",

author = "Masayuki Sato and Zentaro Sakai and Ryusuke Egawa and Hiroaki Kobayashi",

year = "2017",

month = jun,

day = "12",

doi = "10.1109/CoolChips.2017.7946380",

language = "English",

series = "Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017",

note = "20th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017 ; Conference date: 19-04-2017 Through 21-04-2017",

}

TY - GEN

T1 - An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches

AU - Sato, Masayuki

AU - Sakai, Zentaro

AU - Egawa, Ryusuke

AU - Kobayashi, Hiroaki

PY - 2017/6/12

Y1 - 2017/6/12

N2 - Spin-Transfer Torque RAM (STT-RAM) has a higher density than SRAM and non-volatility, and is expected to be used as the last-level cache (LLC) of a microprocessor. One technical issue is that, since the energy cost of write access requests for an STT-RAM LLC is expensive, the total energy consumption of the STT-RAM LLC may increase for some write-intensive applications. Therefore, this paper proposes an Adjacent-Line-Merging Writeback Scheme. The proposed scheme dynamically merges two adjacent lines and write them back to the STT-RAM LLC as one line. The evaluation results show that the proposed scheme can reduce the energy consumption by up to 28%, and 10.4% on average.

AB - Spin-Transfer Torque RAM (STT-RAM) has a higher density than SRAM and non-volatility, and is expected to be used as the last-level cache (LLC) of a microprocessor. One technical issue is that, since the energy cost of write access requests for an STT-RAM LLC is expensive, the total energy consumption of the STT-RAM LLC may increase for some write-intensive applications. Therefore, this paper proposes an Adjacent-Line-Merging Writeback Scheme. The proposed scheme dynamically merges two adjacent lines and write them back to the STT-RAM LLC as one line. The evaluation results show that the proposed scheme can reduce the energy consumption by up to 28%, and 10.4% on average.

KW - STT-RAM cache

KW - cache memory

KW - merged writeback

KW - write energy

UR - http://www.scopus.com/inward/record.url?scp=85022229925&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85022229925&partnerID=8YFLogxK

U2 - 10.1109/CoolChips.2017.7946380

DO - 10.1109/CoolChips.2017.7946380

M3 - Conference contribution

AN - SCOPUS:85022229925

T3 - Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017

BT - Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 20th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017

Y2 - 19 April 2017 through 21 April 2017

ER -

An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches

Abstract

Publication series

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Keywords

ASJC Scopus subject areas

UN SDGs

Access to Document

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