An accurate model of fully-depleted surrounding gate transistor (FD-SGT)

Tetsuo Endoh, Tairiku Nakmura, Fujio Masuoka

Research output: Contribution to journalArticle

47 Citations (Scopus)

Abstract

A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) is analyzed. First, the new gate oxide capacitance model and the new threshold voltage model of FD-SGT are proposed. It is shown that the gate oxide capacitance per unit area increases with scaling down the silicon pillar's diameter. It is newly found that the threshold voltage decreases with scaling down the silicon pillar's diameter, because the gate oxide electric fields increase with increasing gate oxide capacitance. Next, by using the proposed models, the new current-voltage characteristics equation of FD-SGT is analytically formulated for the first time. In comparison with the results of the three-dimensional (3D) device simulator, the results of the new threshold voltage model show good agreement within 0.012V error in maximum. The results of the newly formulated current-voltage characteristics also show good agreement within 1.4% average error. The results of this work make it possible to theoretically clear the device designs of FD-SGT and show the new viewpoints for future ULSI's with SGT.

Original languageEnglish
Pages (from-to)905-909
Number of pages5
JournalIEICE Transactions on Electronics
VolumeE80-C
Issue number7
Publication statusPublished - 1997 Jan 1

Keywords

  • Current-voltage clmracteristics
  • FD-SGT
  • SGT
  • Threshold \vltage

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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