Algorithm-level optimization of multiple-valued arithmetic circuits using counter tree diagrams

Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

This paper presents a novel approach to designing multiple-valued arithmetic circuits based on a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). By using CTDs, we can derive possible variations of addition algorithms in a systematic way without using specific knowledge about underlying arithmetic fundamentals. For any weighted number system, we can design the optimal adder structure by trying every possible CTD representation. In this paper, the potential of the CTD-based method is demonstrated through an experimental design of the Redundant-Binary (RB) adder in multiple-valued current-mode logic. We successfully obtained the RB adder that achieves about 32-57% higher performance in terms of power-delay product compared with the conventional designs.

Original languageEnglish
Title of host publication37th International Symposium on Multiple-Valued Logic, ISMVL 2007
DOIs
Publication statusPublished - 2007 Sep 3
Event37th International Symposium on Multiple-Valued Logic, ISMVL 2007 - Oslo, Norway
Duration: 2007 May 132007 May 16

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other37th International Symposium on Multiple-Valued Logic, ISMVL 2007
CountryNorway
CityOslo
Period07/5/1307/5/16

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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