Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic

Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper presents an algorithm-level interpretation of fast adder structures in binary/multiple-valued logic. The key idea is to employ a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). The use of CTDs makes it possible to represent various addition algorithms for any positional number system. In this paper, we introduce an extension of CTDs for representing possible fast addition algorithms with redundant number systems. Using the extended version of CTDs, we can classify the conventional fast adder structures including those using emerging multiple-valued logic devices into three types in a systematic way.

Original languageEnglish
Title of host publication36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
Number of pages1
DOIs
Publication statusPublished - 2006 Nov 21
Event36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006 - Singapore, Singapore
Duration: 2006 May 172006 May 20

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
CountrySingapore
CitySingapore
Period06/5/1706/5/20

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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