Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories

Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Takahiro Hanyu, Warren J. Gross

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In this paper, a context-driven search engine is presented based on a new family of associative memories. It stores only the associations between items from multiple search fields in the form of binary links, and merges repeated field items to reduce the memory requirements. It achieves 13.6× reduction in memory bits and accesses, and 8.6× reduced number of clock cycles in search operation compared to a classical field-based search structure using content-addressable memory. Furthermore, using parallel computational nodes in the proposed search engine, it achieves five orders of magnitude reduced number of clock cycles compared to a CPU-based counterpart running a classical search algorithm in software.

Original languageEnglish
Title of host publicationIEEE Workshop on Signal Processing Systems, SiPS
Subtitle of host publicationDesign and Implementation
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479965885
DOIs
Publication statusPublished - 2014 Dec 15
Event2014 IEEE Workshop on Signal Processing Systems, SiPS 2014 - Belfast, United Kingdom
Duration: 2014 Oct 202014 Oct 22

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)1520-6130

Other

Other2014 IEEE Workshop on Signal Processing Systems, SiPS 2014
CountryUnited Kingdom
CityBelfast
Period14/10/2014/10/22

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture

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    Jarollahi, H., Onizawa, N., Gripon, V., Hanyu, T., & Gross, W. J. (2014). Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories. In IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation [6986075] (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SiPS.2014.6986075