TY - GEN
T1 - Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories
AU - Jarollahi, Hooman
AU - Onizawa, Naoya
AU - Gripon, Vincent
AU - Hanyu, Takahiro
AU - Gross, Warren J.
PY - 2014/12/15
Y1 - 2014/12/15
N2 - In this paper, a context-driven search engine is presented based on a new family of associative memories. It stores only the associations between items from multiple search fields in the form of binary links, and merges repeated field items to reduce the memory requirements. It achieves 13.6× reduction in memory bits and accesses, and 8.6× reduced number of clock cycles in search operation compared to a classical field-based search structure using content-addressable memory. Furthermore, using parallel computational nodes in the proposed search engine, it achieves five orders of magnitude reduced number of clock cycles compared to a CPU-based counterpart running a classical search algorithm in software.
AB - In this paper, a context-driven search engine is presented based on a new family of associative memories. It stores only the associations between items from multiple search fields in the form of binary links, and merges repeated field items to reduce the memory requirements. It achieves 13.6× reduction in memory bits and accesses, and 8.6× reduced number of clock cycles in search operation compared to a classical field-based search structure using content-addressable memory. Furthermore, using parallel computational nodes in the proposed search engine, it achieves five orders of magnitude reduced number of clock cycles compared to a CPU-based counterpart running a classical search algorithm in software.
UR - http://www.scopus.com/inward/record.url?scp=84920268102&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84920268102&partnerID=8YFLogxK
U2 - 10.1109/SiPS.2014.6986075
DO - 10.1109/SiPS.2014.6986075
M3 - Conference contribution
AN - SCOPUS:84920268102
T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
BT - IEEE Workshop on Signal Processing Systems, SiPS
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2014 IEEE Workshop on Signal Processing Systems, SiPS 2014
Y2 - 20 October 2014 through 22 October 2014
ER -