Abstract
We propose a low-power content-addressable memory (CAM) employing a new algorithm for associativity between the input tag and the corresponding address of the output data. The proposed architecture is based on a recently developed sparse clustered network using binary connections that on-average eliminates most of the parallel comparisons performed during a search. Therefore, the dynamic energy consumption of the proposed design is significantly lower compared with that of a conventional low-power CAM design. Given an input tag, the proposed architecture computes a few possibilities for the location of the matched tag and performs the comparisons on them to locate a single valid match. TSMC 65-nm CMOS technology was used for simulation purposes. Following a selection of design parameters, such as the number of CAM entries, the energy consumption and the search delay of the proposed design are 8%, and 26% of that of the conventional NAND architecture, respectively, with a 10% area overhead. A design methodology based on the silicon area and power budgets, and performance requirements is discussed.
Original language | English |
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Article number | 6808477 |
Pages (from-to) | 642-653 |
Number of pages | 12 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 23 |
Issue number | 4 |
DOIs | |
Publication status | Published - 2015 Apr 1 |
Keywords
- Associative memory
- content-addressable memory (CAM)
- low-power computing
- recurrent neural networks
- sparse clustered networks (SCNs)
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering