Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks

Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross

Research output: Contribution to journalArticlepeer-review

21 Citations (Scopus)


We propose a low-power content-addressable memory (CAM) employing a new algorithm for associativity between the input tag and the corresponding address of the output data. The proposed architecture is based on a recently developed sparse clustered network using binary connections that on-average eliminates most of the parallel comparisons performed during a search. Therefore, the dynamic energy consumption of the proposed design is significantly lower compared with that of a conventional low-power CAM design. Given an input tag, the proposed architecture computes a few possibilities for the location of the matched tag and performs the comparisons on them to locate a single valid match. TSMC 65-nm CMOS technology was used for simulation purposes. Following a selection of design parameters, such as the number of CAM entries, the energy consumption and the search delay of the proposed design are 8%, and 26% of that of the conventional NAND architecture, respectively, with a 10% area overhead. A design methodology based on the silicon area and power budgets, and performance requirements is discussed.

Original languageEnglish
Article number6808477
Pages (from-to)642-653
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number4
Publication statusPublished - 2015 Apr 1


  • Associative memory
  • content-addressable memory (CAM)
  • low-power computing
  • recurrent neural networks
  • sparse clustered networks (SCNs)

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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