AEM investigation of interface structure of Y2O 3-Ta2O5 co-doped zirconia buffer layer

Takanori Kiguchi; Naoki Wakiya; Kazuo Shinozaki; Nobuyasu Mizutani

AEM investigation of interface structure of Y₂O ₃-Ta₂O₅ co-doped zirconia buffer layer

Takanori Kiguchi, Naoki Wakiya, Kazuo Shinozaki, Nobuyasu Mizutani

Research output: Contribution to journal › Conference article › peer-review

Abstract

The effect of Ta doping on the growth of the SiOx layer in YSZ/Si gate dielectrics has been investigated by Analytical TEM (AEM) method. Most part of the YTaSZ layer has epitaxially grown like as YSZ layer. Capacitance-voltage (C-V) hysteresis of YTaSZ film has been suppressed perfectly. It has been, however, that the SiOx thickness of Ta doped YSZ/Si became thicker than YSZ/Si, and that the roughness of the interface between SiOx/Si has been increased. Density of interface trapped charge has been also increased. HRTEM and TEM-EDS analysis has revealed that some of the doped Ta was diffused into SiOx interface layer and the surface of Si substrate, which is thought to be the cause of interface trapped charge.

Original language	English
Pages (from-to)	237-240
Number of pages	4
Journal	Key Engineering Materials
Volume	269
Publication status	Published - 2004 Jan 1
Externally published	Yes
Event	Proceedings of the 23rd Electronics Division Meeting of the Ceramic Society of Japan - Kawasaki, Japan Duration: 2003 Oct 23 → 2003 Oct 24

Keywords

Buffer layer
C-V characteristics
Depth profile
Interface trapped charge
SiO
TEM
TaO
Zirconia

ASJC Scopus subject areas

Materials Science(all)
Mechanics of Materials
Mechanical Engineering

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@article{2aa81b04e52442a3bb03ffc62cba8540,

title = "AEM investigation of interface structure of Y2O 3-Ta2O5 co-doped zirconia buffer layer",

abstract = "The effect of Ta doping on the growth of the SiOx layer in YSZ/Si gate dielectrics has been investigated by Analytical TEM (AEM) method. Most part of the YTaSZ layer has epitaxially grown like as YSZ layer. Capacitance-voltage (C-V) hysteresis of YTaSZ film has been suppressed perfectly. It has been, however, that the SiOx thickness of Ta doped YSZ/Si became thicker than YSZ/Si, and that the roughness of the interface between SiOx/Si has been increased. Density of interface trapped charge has been also increased. HRTEM and TEM-EDS analysis has revealed that some of the doped Ta was diffused into SiOx interface layer and the surface of Si substrate, which is thought to be the cause of interface trapped charge.",

keywords = "Buffer layer, C-V characteristics, Depth profile, Interface trapped charge, SiO, TEM, TaO, Zirconia",

author = "Takanori Kiguchi and Naoki Wakiya and Kazuo Shinozaki and Nobuyasu Mizutani",

year = "2004",

month = jan,

day = "1",

language = "English",

volume = "269",

pages = "237--240",

journal = "Key Engineering Materials",

issn = "1013-9826",

publisher = "Trans Tech Publications",

note = "Proceedings of the 23rd Electronics Division Meeting of the Ceramic Society of Japan ; Conference date: 23-10-2003 Through 24-10-2003",

}

TY - JOUR

T1 - AEM investigation of interface structure of Y2O 3-Ta2O5 co-doped zirconia buffer layer

AU - Kiguchi, Takanori

AU - Wakiya, Naoki

AU - Shinozaki, Kazuo

AU - Mizutani, Nobuyasu

PY - 2004/1/1

Y1 - 2004/1/1

N2 - The effect of Ta doping on the growth of the SiOx layer in YSZ/Si gate dielectrics has been investigated by Analytical TEM (AEM) method. Most part of the YTaSZ layer has epitaxially grown like as YSZ layer. Capacitance-voltage (C-V) hysteresis of YTaSZ film has been suppressed perfectly. It has been, however, that the SiOx thickness of Ta doped YSZ/Si became thicker than YSZ/Si, and that the roughness of the interface between SiOx/Si has been increased. Density of interface trapped charge has been also increased. HRTEM and TEM-EDS analysis has revealed that some of the doped Ta was diffused into SiOx interface layer and the surface of Si substrate, which is thought to be the cause of interface trapped charge.

AB - The effect of Ta doping on the growth of the SiOx layer in YSZ/Si gate dielectrics has been investigated by Analytical TEM (AEM) method. Most part of the YTaSZ layer has epitaxially grown like as YSZ layer. Capacitance-voltage (C-V) hysteresis of YTaSZ film has been suppressed perfectly. It has been, however, that the SiOx thickness of Ta doped YSZ/Si became thicker than YSZ/Si, and that the roughness of the interface between SiOx/Si has been increased. Density of interface trapped charge has been also increased. HRTEM and TEM-EDS analysis has revealed that some of the doped Ta was diffused into SiOx interface layer and the surface of Si substrate, which is thought to be the cause of interface trapped charge.

KW - Buffer layer

KW - C-V characteristics

KW - Depth profile

KW - Interface trapped charge

KW - SiO

KW - TEM

KW - TaO

KW - Zirconia

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M3 - Conference article

AN - SCOPUS:8644237456

VL - 269

SP - 237

EP - 240

JO - Key Engineering Materials

JF - Key Engineering Materials

SN - 1013-9826

T2 - Proceedings of the 23rd Electronics Division Meeting of the Ceramic Society of Japan

Y2 - 23 October 2003 through 24 October 2003

ER -