Advanced FinFET process technology for 20 nm node and beyond

M. Masahara; T. Matsukawa; K. Endo; Y. X. Liu; W. Mizubayashi; S. Migita; S. O'Uchi; H. Ota; Y. Morita

doi:10.1109/INEC.2011.5991771

Advanced FinFET process technology for 20 nm node and beyond

M. Masahara, T. Matsukawa, K. Endo, Y. X. Liu, W. Mizubayashi, S. Migita, S. O'Uchi, H. Ota, Y. Morita

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

One of the biggest challenges for the VLSI circuits with 20-nm-technology nodes and beyond is to overcome the issue of a catastrophic increase in power dissipation of the circuit due to short channel effects (SCEs). Fortunately, double-gate FinFETs have a promising potential to overcome this issue due to their superior SCE immunity even with an undoped channel thanks to the 3D structure. This paper presents novel FinFET process technologies for 20 nm node and beyond.

Original language	English
Title of host publication	4th IEEE International NanoElectronics Conference, INEC 2011
DOIs	https://doi.org/10.1109/INEC.2011.5991771
Publication status	Published - 2011 Sep 26
Externally published	Yes
Event	4th IEEE International Nanoelectronics Conference, INEC 2011 - Tao-Yuan, Taiwan, Province of China Duration: 2011 Jun 21 → 2011 Jun 24

Publication series

Name	Proceedings - International NanoElectronics Conference, INEC
ISSN (Print)	2159-3523

Other

Other	4th IEEE International Nanoelectronics Conference, INEC 2011
Country/Territory	Taiwan, Province of China
City	Tao-Yuan
Period	11/6/21 → 11/6/24

Keywords

FinFET
Metal Gate
Metal S/D
NiSi
Wet Etching

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/INEC.2011.5991771

Cite this

Advanced FinFET process technology for 20 nm node and beyond. / Masahara, M.; Matsukawa, T.; Endo, K.; Liu, Y. X.; Mizubayashi, W.; Migita, S.; O'Uchi, S.; Ota, H.; Morita, Y.

4th IEEE International NanoElectronics Conference, INEC 2011. 2011. 5991771 (Proceedings - International NanoElectronics Conference, INEC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Masahara, M, Matsukawa, T, Endo, K, Liu, YX, Mizubayashi, W, Migita, S, O'Uchi, S, Ota, H & Morita, Y 2011, Advanced FinFET process technology for 20 nm node and beyond. in 4th IEEE International NanoElectronics Conference, INEC 2011., 5991771, Proceedings - International NanoElectronics Conference, INEC, 4th IEEE International Nanoelectronics Conference, INEC 2011, Tao-Yuan, Taiwan, Province of China, 11/6/21. https://doi.org/10.1109/INEC.2011.5991771

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title = "Advanced FinFET process technology for 20 nm node and beyond",

abstract = "One of the biggest challenges for the VLSI circuits with 20-nm-technology nodes and beyond is to overcome the issue of a catastrophic increase in power dissipation of the circuit due to short channel effects (SCEs). Fortunately, double-gate FinFETs have a promising potential to overcome this issue due to their superior SCE immunity even with an undoped channel thanks to the 3D structure. This paper presents novel FinFET process technologies for 20 nm node and beyond.",

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language = "English",

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series = "Proceedings - International NanoElectronics Conference, INEC",

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AU - Matsukawa, T.

AU - Endo, K.

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AU - Migita, S.

AU - O'Uchi, S.

AU - Ota, H.

AU - Morita, Y.

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AB - One of the biggest challenges for the VLSI circuits with 20-nm-technology nodes and beyond is to overcome the issue of a catastrophic increase in power dissipation of the circuit due to short channel effects (SCEs). Fortunately, double-gate FinFETs have a promising potential to overcome this issue due to their superior SCE immunity even with an undoped channel thanks to the 3D structure. This paper presents novel FinFET process technologies for 20 nm node and beyond.

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KW - Wet Etching

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Advanced FinFET process technology for 20 nm node and beyond

Abstract

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Keywords

ASJC Scopus subject areas

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