@inproceedings{21666a3468b74317b6b565e7fee3d312,
title = "Advanced FinFET process technology for 20 nm node and beyond",
abstract = "One of the biggest challenges for the VLSI circuits with 20-nm-technology nodes and beyond is to overcome the issue of a catastrophic increase in power dissipation of the circuit due to short channel effects (SCEs). Fortunately, double-gate FinFETs have a promising potential to overcome this issue due to their superior SCE immunity even with an undoped channel thanks to the 3D structure. This paper presents novel FinFET process technologies for 20 nm node and beyond.",
keywords = "FinFET, Metal Gate, Metal S/D, NiSi, Wet Etching",
author = "M. Masahara and T. Matsukawa and K. Endo and Liu, {Y. X.} and W. Mizubayashi and S. Migita and S. O'Uchi and H. Ota and Y. Morita",
year = "2011",
month = sep,
day = "26",
doi = "10.1109/INEC.2011.5991771",
language = "English",
isbn = "9781457703799",
series = "Proceedings - International NanoElectronics Conference, INEC",
booktitle = "4th IEEE International NanoElectronics Conference, INEC 2011",
note = "4th IEEE International Nanoelectronics Conference, INEC 2011 ; Conference date: 21-06-2011 Through 24-06-2011",
}