A new gate-level power-gating scheme with a small power-gating controller is proposed for greedily power-aware asynchronous pipelined system. The power supply of each standby stage consisting of a combinational block and a pipeline latch can be cut off by a sleep transistor, because a condition of an asynchronous operation is always monitored by using signal conditions in adjacent stages, which completely eliminates wasted power dissipation in standby stages. Since sleep-transistor control signals in each stage are simply generated by just modifying asynchronous control signals in its adjacent stage, the power-gating controller can be realized by inserting a few basic logic gates. The efficiency of the proposed scheme is demonstrated by using HSPICE simulation. The leakage power dissipation of the asynchronous circuit using the proposed method is reduced to 11.8% in comparison with that of the asynchronous one using a conventional power-gating method.