TY - GEN
T1 - Achieving low vT Ni-FUSI CMOS via lanthanide incorporation in the gate stack
AU - Veloso, A.
AU - Yu, H. Y.
AU - Lauwers, A.
AU - Chang, S. Z.
AU - Adelmann, C.
AU - Onsia, B.
AU - Demand, M.
AU - Brus, S.
AU - Vrancken, C.
AU - Singanamalla, R.
AU - Lehnen, P.
AU - Kittl, J.
AU - Kauerauf, T.
AU - Vos, R.
AU - O'Sullivan, B. J.
AU - Van Elshocht, S.
AU - Mitsuhashi, R.
AU - Whittemore, G.
AU - Yin, K. M.
AU - Niwa, M.
AU - Hoffmann, T.
AU - Absil, P.
AU - Jurczak, M.
AU - Biesemans, S.
PY - 2007/1/1
Y1 - 2007/1/1
N2 - This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (WF) modulation towards n-type band-edge for Ni-FUSI devices. This is done by: a) deposition of a Dy2O3 capping layer on the host dielectric (SiON or HfSiON), or b) simple Yb implantation of nMOS poly gates prior to FUSI. We show that: 1) both cases result in dielectric modification with gate leakage (JG) reduction; 2) adding a cap has no significant impact on Tinv (<1Å), while up to ∼5 and 2Å reduction occurs for SiON and HfSiON Yb-implanted devices, respectively; 3) the largest J G reduction (150×) is obtained for capped SiON devices due to dielectric intermixing and formation of a new high-k dielectric (DySiON), comparable to HfSiON in JG and mobility but with 500mV smaller V T; 4) on the other hand, being less invasive to the host dielectric, the optimized Yb I/I option gives 18% improved mobility compared to capped SiON devices; 5) excellent process control and reliability behavior (VT instability by a.c. pulsed IV, PBTI and TDDB) is reported for both WF tuning methods. They allow AWF(n-p) values up to ∼800meV when combined with Ni-silicide FUSI phase engineering, promising for low-VT CMOS.
AB - This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (WF) modulation towards n-type band-edge for Ni-FUSI devices. This is done by: a) deposition of a Dy2O3 capping layer on the host dielectric (SiON or HfSiON), or b) simple Yb implantation of nMOS poly gates prior to FUSI. We show that: 1) both cases result in dielectric modification with gate leakage (JG) reduction; 2) adding a cap has no significant impact on Tinv (<1Å), while up to ∼5 and 2Å reduction occurs for SiON and HfSiON Yb-implanted devices, respectively; 3) the largest J G reduction (150×) is obtained for capped SiON devices due to dielectric intermixing and formation of a new high-k dielectric (DySiON), comparable to HfSiON in JG and mobility but with 500mV smaller V T; 4) on the other hand, being less invasive to the host dielectric, the optimized Yb I/I option gives 18% improved mobility compared to capped SiON devices; 5) excellent process control and reliability behavior (VT instability by a.c. pulsed IV, PBTI and TDDB) is reported for both WF tuning methods. They allow AWF(n-p) values up to ∼800meV when combined with Ni-silicide FUSI phase engineering, promising for low-VT CMOS.
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U2 - 10.1109/ESSDERC.2007.4430912
DO - 10.1109/ESSDERC.2007.4430912
M3 - Conference contribution
AN - SCOPUS:39549091906
SN - 1424411238
SN - 9781424411238
T3 - ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference
SP - 195
EP - 198
BT - ESSDERC07 - 2007 37th European Solid State Device Research Conference
PB - IEEE Computer Society
T2 - ESSDERC 2007 - 37th European Solid-State Device Research Conference
Y2 - 11 September 2007 through 13 September 2007
ER -