Achieving low v_T Ni-FUSI CMOS via lanthanide incorporation in the gate stack

This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (WF) modulation towards n-type band-edge for Ni-FUSI devices. This is done by: a) deposition of a Dy₂O₃ capping layer on the host dielectric (SiON or HfSiON), or b) simple Yb implantation of nMOS poly gates prior to FUSI. We show that: 1) both cases result in dielectric modification with gate leakage (J_G) reduction; 2) adding a cap has no significant impact on T_inv (<1Å), while up to ∼5 and 2Å reduction occurs for SiON and HfSiON Yb-implanted devices, respectively; 3) the largest J _G reduction (150×) is obtained for capped SiON devices due to dielectric intermixing and formation of a new high-k dielectric (DySiON), comparable to HfSiON in J_G and mobility but with 500mV smaller V _T; 4) on the other hand, being less invasive to the host dielectric, the optimized Yb I/I option gives 18% improved mobility compared to capped SiON devices; 5) excellent process control and reliability behavior (VT instability by a.c. pulsed IV, PBTI and TDDB) is reported for both WF tuning methods. They allow AWF(n-p) values up to ∼800meV when combined with Ni-silicide FUSI phase engineering, promising for low-V_T CMOS.