Achieving low vT Ni-FUSI CMOS via lanthanide incorporation in the gate stack

A. Veloso, H. Y. Yu, A. Lauwers, S. Z. Chang, C. Adelmann, B. Onsia, M. Demand, S. Brus, C. Vrancken, R. Singanamalla, P. Lehnen, J. Kittl, T. Kauerauf, R. Vos, B. J. O'Sullivan, S. Van Elshocht, R. Mitsuhashi, G. Whittemore, K. M. Yin, M. NiwaT. Hoffmann, P. Absil, M. Jurczak, S. Biesemans

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (WF) modulation towards n-type band-edge for Ni-FUSI devices. This is done by: a) deposition of a Dy2O3 capping layer on the host dielectric (SiON or HfSiON), or b) simple Yb implantation of nMOS poly gates prior to FUSI. We show that: 1) both cases result in dielectric modification with gate leakage (JG) reduction; 2) adding a cap has no significant impact on Tinv (<1Å), while up to ∼5 and 2Å reduction occurs for SiON and HfSiON Yb-implanted devices, respectively; 3) the largest J G reduction (150×) is obtained for capped SiON devices due to dielectric intermixing and formation of a new high-k dielectric (DySiON), comparable to HfSiON in JG and mobility but with 500mV smaller V T; 4) on the other hand, being less invasive to the host dielectric, the optimized Yb I/I option gives 18% improved mobility compared to capped SiON devices; 5) excellent process control and reliability behavior (VT instability by a.c. pulsed IV, PBTI and TDDB) is reported for both WF tuning methods. They allow AWF(n-p) values up to ∼800meV when combined with Ni-silicide FUSI phase engineering, promising for low-VT CMOS.

Original languageEnglish
Title of host publicationESSDERC07 - 2007 37th European Solid State Device Research Conference
PublisherIEEE Computer Society
Pages195-198
Number of pages4
ISBN (Print)1424411238, 9781424411238
DOIs
Publication statusPublished - 2007 Jan 1
Externally publishedYes
EventESSDERC 2007 - 37th European Solid-State Device Research Conference - Munich, Germany
Duration: 2007 Sep 112007 Sep 13

Publication series

NameESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference
Volume2007

Other

OtherESSDERC 2007 - 37th European Solid-State Device Research Conference
CountryGermany
CityMunich
Period07/9/1107/9/13

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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  • Cite this

    Veloso, A., Yu, H. Y., Lauwers, A., Chang, S. Z., Adelmann, C., Onsia, B., Demand, M., Brus, S., Vrancken, C., Singanamalla, R., Lehnen, P., Kittl, J., Kauerauf, T., Vos, R., O'Sullivan, B. J., Van Elshocht, S., Mitsuhashi, R., Whittemore, G., Yin, K. M., ... Biesemans, S. (2007). Achieving low vT Ni-FUSI CMOS via lanthanide incorporation in the gate stack. In ESSDERC07 - 2007 37th European Solid State Device Research Conference (pp. 195-198). [4430912] (ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference; Vol. 2007). IEEE Computer Society. https://doi.org/10.1109/ESSDERC.2007.4430912