Accurate asynchronous network-on-chip simulation based on a delay-aware model

Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

A performance-evaluation simulator, such as a cycle-accurate simulator, is a key tool for exploring appropriate asynchronous Network-on-Chip (NoC) architectures in early stages of VLSI design, but its accuracy is insufficient in practical VLSI implementation. In this paper, a highly accurate performance-evaluation simulator based on a delay-aware model is proposed for implementing an appropriate asynchronous NoC system. While the unit delay between circuit blocks at every pipeline stage is constant in the conventional cycle-accurate simulator, which causes poor accuracy, the unit delay between circuit blocks in the proposed approach is determined independently by its desirable logic function. The use of this "delay-aware" model makes it accurate to simulate asynchronous NoC systems. As a design example, a 16-core asynchronous Spidergon NoC system is simulated by the conventional cycle-accurate and the proposed simulator whose results, such as latency and throughput, are validated with a highly precise transistor-level simulation result. As a result, the proposed simulator achieves almost the same accuracy as one of the transistor-level simulators with the simulation speed comparable to the cycle-accurate simulator.

Original languageEnglish
Title of host publicationProceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010
Pages357-362
Number of pages6
DOIs
Publication statusPublished - 2010 Oct 20
EventIEEE Annual Symposium on VLSI, ISVLSI 2010 - Lixouri, Kefalonia, Greece
Duration: 2010 Jul 52010 Jul 7

Publication series

NameProceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010

Other

OtherIEEE Annual Symposium on VLSI, ISVLSI 2010
CountryGreece
CityLixouri, Kefalonia
Period10/7/510/7/7

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Onizawa, N., Funazaki, T., Matsumoto, A., & Hanyu, T. (2010). Accurate asynchronous network-on-chip simulation based on a delay-aware model. In Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010 (pp. 357-362). [5572802] (Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010). https://doi.org/10.1109/ISVLSI.2010.45