Accurate asynchronous network-on-chip simulation based on a delay-aware model

Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

A performance-evaluation simulator, such as a cycle-accurate simulator, is a key tool for exploring appropriate asynchronous Network-on-Chip (NoC) architectures in early stages of VLSI design, but its accuracy is insufficient in practical VLSI implementation. In this paper, a highly accurate performance-evaluation simulator based on a delay-aware model is proposed for implementing an appropriate asynchronous NoC system. While the unit delay between circuit blocks at every pipeline stage is constant in the conventional cycle-accurate simulator, which causes poor accuracy, the unit delay between circuit blocks in the proposed approach is determined independently by its desirable logic function. The use of this "delay-aware" model makes it accurate to simulate asynchronous NoC systems. As a design example, a 16-core asynchronous Spidergon NoC system is simulated by the conventional cycle-accurate and the proposed simulator whose results, such as latency and throughput, are validated with a highly precise transistor-level simulation result. As a result, the proposed simulator achieves almost the same accuracy as one of the transistor-level simulators with the simulation speed comparable to the cycle-accurate simulator.

Original languageEnglish
Title of host publicationVLSI 2010 Annual Symposium
Subtitle of host publicationSelected papers
EditorsNikolaos Voros, Amar Mukherjee, Nicolas Sklavos, Konstantinos Masselos, Michael Huebner
Pages17-30
Number of pages14
DOIs
Publication statusPublished - 2011

Publication series

NameLecture Notes in Electrical Engineering
Volume105 LNEE
ISSN (Print)1876-1100
ISSN (Electronic)1876-1119

ASJC Scopus subject areas

  • Industrial and Manufacturing Engineering

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