Accurate and high-speed asynchronous network-on-chip simulation using physical wire-delay information

Takahiro Hanyu, Yuma Watanabe, Atsushi Matsumoto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A performance-evaluation simulator is a key tool for exploring appropriate asynchronous Network-on-Chip (NoC) architecture in early stage of LSI design. This paper presents a highly accurate performance-evaluation simulator with maintaining a short evaluation time for designing a high-performance asynchronous NoC. The use of a precise asynchronous-router circuit model, whose physical parameters such as wire delays as well as unit gate delays are preliminarily obtained using LSI CAD tool, makes it accurate to simulate asynchronous NoC systems. As a design example, multi-core asynchronous mesh-structured NoC systems are simulated by both the previous method and the proposed one whose results, such as latency and throughput, are validated with a highly precise transistor-level simulation result. As a result, the proposed simulator achieves almost the same accuracy as the corresponding gate-level simulators, while its simulation speed is one-thousand-times faster than that of the gate-level one at the packet injection rate of 30 (packets/sec).

Original languageEnglish
Title of host publicationProceedings - 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013
Pages266-271
Number of pages6
DOIs
Publication statusPublished - 2013 Aug 1
Event2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013 - Toyama, Japan
Duration: 2013 May 222013 May 24

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013
CountryJapan
CityToyama
Period13/5/2213/5/24

Keywords

  • LSI CAD tool
  • asynchronous network-on-chip (NoC)
  • computation time
  • network topology

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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