Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL

Hasitha Muthumala Waidyasooriya; Yusuke Araki; Masanori Hariyama

doi:10.1109/ISPACS.2018.8923263

Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL

Hasitha Muthumala Waidyasooriya, Yusuke Araki, Masanori Hariyama

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Quantum annealing (QA) is used to find the global optimum for combinatorial optimization problems. QA can be simulated on a computer using quantum Monte Carlo (QMC) simulation while spending a huge processing time. We propose a custom architecture to accelerate simulated QA. The proposed architecture is implemented using 'open computing language (OpenCL)' on an Intel Aria10 FPGA. It is possible to design the most appropriate architecture for different optimization problems by changing the design parameters of the OpenCL code. We achieved over 1.94 times speed-up compared to CPU-based implementation.

Original language	English
Title of host publication	ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	335-340
Number of pages	6
ISBN (Electronic)	9781538657713
DOIs	https://doi.org/10.1109/ISPACS.2018.8923263
Publication status	Published - 2018 Nov
Event	2018 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2018 - Ishigaki Island, Okinawa, Japan Duration: 2018 Nov 27 → 2018 Nov 30

Publication series

Name	ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems

Conference

Conference	2018 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2018
Country/Territory	Japan
City	Ishigaki Island, Okinawa
Period	18/11/27 → 18/11/30

Keywords

OpenCL for FPGA
Simulated quantum annealing
combinatorial optimization problems
hardware acceleration

ASJC Scopus subject areas

Artificial Intelligence
Computer Networks and Communications
Computer Science Applications
Signal Processing

Access to Document

10.1109/ISPACS.2018.8923263

Cite this

Waidyasooriya, H. M., Araki, Y., & Hariyama, M. (2018). Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL. In ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems (pp. 335-340). [8923263] (ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISPACS.2018.8923263

Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL. / Waidyasooriya, Hasitha Muthumala; Araki, Yusuke; Hariyama, Masanori.

ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems. Institute of Electrical and Electronics Engineers Inc., 2018. p. 335-340 8923263 (ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Waidyasooriya, HM, Araki, Y & Hariyama, M 2018, Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL. in ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems., 8923263, ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems, Institute of Electrical and Electronics Engineers Inc., pp. 335-340, 2018 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2018, Ishigaki Island, Okinawa, Japan, 18/11/27. https://doi.org/10.1109/ISPACS.2018.8923263

Waidyasooriya HM, Araki Y, Hariyama M. Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL. In ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems. Institute of Electrical and Electronics Engineers Inc. 2018. p. 335-340. 8923263. (ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems). https://doi.org/10.1109/ISPACS.2018.8923263

Waidyasooriya, Hasitha Muthumala ; Araki, Yusuke ; Hariyama, Masanori. / Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL. ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 335-340 (ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems).

@inproceedings{e67b10fb93c94ff48ea71d81e2dd3942,

title = "Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL",

abstract = "Quantum annealing (QA) is used to find the global optimum for combinatorial optimization problems. QA can be simulated on a computer using quantum Monte Carlo (QMC) simulation while spending a huge processing time. We propose a custom architecture to accelerate simulated QA. The proposed architecture is implemented using 'open computing language (OpenCL)' on an Intel Aria10 FPGA. It is possible to design the most appropriate architecture for different optimization problems by changing the design parameters of the OpenCL code. We achieved over 1.94 times speed-up compared to CPU-based implementation.",

keywords = "OpenCL for FPGA, Simulated quantum annealing, combinatorial optimization problems, hardware acceleration",

author = "Waidyasooriya, {Hasitha Muthumala} and Yusuke Araki and Masanori Hariyama",

year = "2018",

month = nov,

doi = "10.1109/ISPACS.2018.8923263",

language = "English",

series = "ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "335--340",

booktitle = "ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems",

note = "2018 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2018 ; Conference date: 27-11-2018 Through 30-11-2018",

}

TY - GEN

T1 - Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL

AU - Waidyasooriya, Hasitha Muthumala

AU - Araki, Yusuke

AU - Hariyama, Masanori

PY - 2018/11

Y1 - 2018/11

N2 - Quantum annealing (QA) is used to find the global optimum for combinatorial optimization problems. QA can be simulated on a computer using quantum Monte Carlo (QMC) simulation while spending a huge processing time. We propose a custom architecture to accelerate simulated QA. The proposed architecture is implemented using 'open computing language (OpenCL)' on an Intel Aria10 FPGA. It is possible to design the most appropriate architecture for different optimization problems by changing the design parameters of the OpenCL code. We achieved over 1.94 times speed-up compared to CPU-based implementation.

AB - Quantum annealing (QA) is used to find the global optimum for combinatorial optimization problems. QA can be simulated on a computer using quantum Monte Carlo (QMC) simulation while spending a huge processing time. We propose a custom architecture to accelerate simulated QA. The proposed architecture is implemented using 'open computing language (OpenCL)' on an Intel Aria10 FPGA. It is possible to design the most appropriate architecture for different optimization problems by changing the design parameters of the OpenCL code. We achieved over 1.94 times speed-up compared to CPU-based implementation.

KW - OpenCL for FPGA

KW - Simulated quantum annealing

KW - combinatorial optimization problems

KW - hardware acceleration

UR - http://www.scopus.com/inward/record.url?scp=85077043662&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85077043662&partnerID=8YFLogxK

U2 - 10.1109/ISPACS.2018.8923263

DO - 10.1109/ISPACS.2018.8923263

M3 - Conference contribution

AN - SCOPUS:85077043662

T3 - ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems

SP - 335

EP - 340

BT - ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2018

Y2 - 27 November 2018 through 30 November 2018

ER -

Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this