Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Quantum annealing (QA) is used to find the global optimum for combinatorial optimization problems. QA can be simulated on a computer using quantum Monte Carlo (QMC) simulation while spending a huge processing time. We propose a custom architecture to accelerate simulated QA. The proposed architecture is implemented using 'open computing language (OpenCL)' on an Intel Aria10 FPGA. It is possible to design the most appropriate architecture for different optimization problems by changing the design parameters of the OpenCL code. We achieved over 1.94 times speed-up compared to CPU-based implementation.

Original languageEnglish
Title of host publicationISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages335-340
Number of pages6
ISBN (Electronic)9781538657713
DOIs
Publication statusPublished - 2018 Nov
Event2018 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2018 - Ishigaki Island, Okinawa, Japan
Duration: 2018 Nov 272018 Nov 30

Publication series

NameISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems

Conference

Conference2018 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2018
Country/TerritoryJapan
CityIshigaki Island, Okinawa
Period18/11/2718/11/30

Keywords

  • OpenCL for FPGA
  • Simulated quantum annealing
  • combinatorial optimization problems
  • hardware acceleration

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computer Networks and Communications
  • Computer Science Applications
  • Signal Processing

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