TY - JOUR
T1 - Acceleration of block matching on a low-power heterogeneous multi-core processor based on DTU data-transfer with data re-allocation
AU - Hiramatsu, Yoshitaka
AU - Waidyasooriya, Hasitha Muthumala
AU - Hariyama, Masanori
AU - Nojiri, Toru
AU - Uchiyama, Kunio
AU - Kameyama, Michitaka
PY - 2012/12
Y1 - 2012/12
N2 - The large data-transfer time among different cores is a big problem in heterogeneous multi-core processors. This paper presents a method to accelerate the data transfers exploiting data-transfer-units together with complex memory allocation. We used block matching, which is very common in image processing, to evaluate our technique. The proposed method reduces the data-transfer time by more than 42% compared to the earlier works that use CPU-based data transfers. Moreover, the total processing time is only 15ms for a VGA image with 16 × 16 pixel blocks.
AB - The large data-transfer time among different cores is a big problem in heterogeneous multi-core processors. This paper presents a method to accelerate the data transfers exploiting data-transfer-units together with complex memory allocation. We used block matching, which is very common in image processing, to evaluate our technique. The proposed method reduces the data-transfer time by more than 42% compared to the earlier works that use CPU-based data transfers. Moreover, the total processing time is only 15ms for a VGA image with 16 × 16 pixel blocks.
KW - Accelerator
KW - Block matching
KW - Data transfer
KW - Dynamically reconfigurable processor
KW - Heterogeneous multi-core
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U2 - 10.1587/transele.E95.C.1872
DO - 10.1587/transele.E95.C.1872
M3 - Article
AN - SCOPUS:84871232925
VL - E95-C
SP - 1872
EP - 1882
JO - IEICE Transactions on Electronics
JF - IEICE Transactions on Electronics
SN - 0916-8524
IS - 12
ER -