Acceleration of block matching on a low-power heterogeneous multi-core processor based on DTU data-transfer with data re-allocation

Yoshitaka Hiramatsu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Toru Nojiri, Kunio Uchiyama, Michitaka Kameyama

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

The large data-transfer time among different cores is a big problem in heterogeneous multi-core processors. This paper presents a method to accelerate the data transfers exploiting data-transfer-units together with complex memory allocation. We used block matching, which is very common in image processing, to evaluate our technique. The proposed method reduces the data-transfer time by more than 42% compared to the earlier works that use CPU-based data transfers. Moreover, the total processing time is only 15ms for a VGA image with 16 × 16 pixel blocks.

Original languageEnglish
Pages (from-to)1872-1882
Number of pages11
JournalIEICE Transactions on Electronics
VolumeE95-C
Issue number12
DOIs
Publication statusPublished - 2012 Dec

Keywords

  • Accelerator
  • Block matching
  • Data transfer
  • Dynamically reconfigurable processor
  • Heterogeneous multi-core

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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