Acceleration of block matching on a low-power heterogeneous multi-core processor based on DTU data-transfer with data re-allocation

Yoshitaka Hiramatsu; Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Toru Nojiri; Kunio Uchiyama; Michitaka Kameyama

doi:10.1587/transele.E95.C.1872

Acceleration of block matching on a low-power heterogeneous multi-core processor based on DTU data-transfer with data re-allocation

Yoshitaka Hiramatsu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Toru Nojiri, Kunio Uchiyama, Michitaka Kameyama

INF - Computer and Mathematical Sciences

Research output: Contribution to journal › Article

1 Citation (Scopus)

Abstract

The large data-transfer time among different cores is a big problem in heterogeneous multi-core processors. This paper presents a method to accelerate the data transfers exploiting data-transfer-units together with complex memory allocation. We used block matching, which is very common in image processing, to evaluate our technique. The proposed method reduces the data-transfer time by more than 42% compared to the earlier works that use CPU-based data transfers. Moreover, the total processing time is only 15ms for a VGA image with 16 × 16 pixel blocks.

Original language	English
Pages (from-to)	1872-1882
Number of pages	11
Journal	IEICE Transactions on Electronics
Volume	E95-C
Issue number	12
DOIs	https://doi.org/10.1587/transele.E95.C.1872
Publication status	Published - 2012 Dec

Keywords

Accelerator
Block matching
Data transfer
Dynamically reconfigurable processor
Heterogeneous multi-core

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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Hiramatsu, Y., Waidyasooriya, H. M., Hariyama, M., Nojiri, T., Uchiyama, K., & Kameyama, M. (2012). Acceleration of block matching on a low-power heterogeneous multi-core processor based on DTU data-transfer with data re-allocation. IEICE Transactions on Electronics, E95-C(12), 1872-1882. https://doi.org/10.1587/transele.E95.C.1872

Acceleration of block matching on a low-power heterogeneous multi-core processor based on DTU data-transfer with data re-allocation. / Hiramatsu, Yoshitaka; Waidyasooriya, Hasitha Muthumala ; Hariyama, Masanori; Nojiri, Toru; Uchiyama, Kunio; Kameyama, Michitaka.

In: IEICE Transactions on Electronics, Vol. E95-C, No. 12, 12.2012, p. 1872-1882.

Research output: Contribution to journal › Article

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