A WiMAX turbo decoder with tailbiting BIP architecture

Hiroaki Arai, Naoto Miyamoto, Koji Kotani, Hisanori Fujisawa, Takashi Ito

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A tailbiting block-interleaved pipelining (TB-BIP) is proposed for deeply-pipelined turbo decoders. Conventional sliding window block-interleaved pipelining (SW-BIP) turbo decoders suffer from many warm-up calculations when the number of pipeline stages is increased. However, by using TB-BIP, more than 50% of the warm-up calculations are reduced as compared to SW-BIP. We have implemented a TB-BIP WiMAX turbo decoder with four pipeline stages in the area of 3.8 mm2 using a 0.18 μm CMOS technology. The chip achieved 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation.

Original languageEnglish
Title of host publication2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Pages371-372
Number of pages2
DOIs
Publication statusPublished - 2010 Apr 28
Event2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan, Province of China
Duration: 2010 Jan 182010 Jan 21

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
CountryTaiwan, Province of China
CityTaipei
Period10/1/1810/1/21

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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  • Cite this

    Arai, H., Miyamoto, N., Kotani, K., Fujisawa, H., & Ito, T. (2010). A WiMAX turbo decoder with tailbiting BIP architecture. In 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 (pp. 371-372). [5419858] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2010.5419858