A WiMAX turbo decoder with tailbiting BIP architecture

Hiroaki Arai, Naoto Miyamoto, Koji Kotani, Hisanori Fujisawa, Takashi Itoh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, a tailbitlng block-interleaved pipelining (BIP) architecture is proposed for high-throughput and energy efficient WiMAX turbo decoders. Conventional sliding window (SW) BIP turbo decoders suffer from many warm-up calculations and large memory size when the number of pipeline stages is Increased. Instead of the SW, we combined the tailbltlng method with BIP. Consequently, more than 50% of the warm-up calculation was reduced, and necessary memory size became constant. We have implemented a tailbiting BIP WiMAX turbo decoder with 4 pipeline stages in the area of 3.8 mm2 using a 0.18 μm CMOS technology. The chip achieves 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation.

Original languageEnglish
Title of host publicationProceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
Pages377-380
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 - Taipei, Taiwan, Province of China
Duration: 2009 Nov 162009 Nov 18

Publication series

NameProceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Other

Other2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
CountryTaiwan, Province of China
CityTaipei
Period09/11/1609/11/18

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A WiMAX turbo decoder with tailbiting BIP architecture'. Together they form a unique fingerprint.

Cite this